SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 135
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SAM9M11
Manufacturer Part Number
SAM9M11
Description
Manufacturer
Atmel Corporation
Specifications of SAM9M11
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Dac Resolution (bits)
No
Temp. Sensor
No
Crypto Engine
AES/DES
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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5.5.6
ARM DDI0198D
Integrating RAM test logic
The memory used to implement TCM might require some form of test access, typically
by a BIST controller. Generally this is done by adding a collar of multiplexors around
the memory inputs. However, this method will add undesirable delays to the chip select
and address signals. This can be avoided by using the DMA interface to perform the
multiplexing of address and chip-select values. This is shown in Figure 5-19 on
page 5-28.
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRDMAADDR[17:0]
Figure 5-18 TCM subsystem that uses the DMA interface
DRADDR[17:0]
ARM926EJ-S
DRWD[31:0]
DRWBL[3:0]
DRRD[31:0]
DRDMAEN
DRDMACS
DRWAIT
DRSEQ
DRnRW
DRCS
Tightly-Coupled Memory Interface
1
0
1
0
1
0
DMAADDR[31:0]
DRDMAEN
DMAWD[31:0]
DMAnRW
DMAWBL[3:0]
DMARD[31:0]
RD[31:0]
WBL[3:0]
nRW
WD[31:0]
A[17:0]
CS
DMA
SRAM
5-27
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