SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 111

no-image

SAM9X35

Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9X35

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Tightly-Coupled Memory Interface
memory. The TCM interface contains a two entry write buffer, which avoids the need
for stall cycles because of the mismatch between the ARM9EJ-S native memory
interface, and the requirements for standard SRAM.
TCM accesses can be extended by using the IRWAIT/DRWAIT inputs to generate wait
states. However, the timing of these and other interface signals is such that the types of
memory sub-systems that can be implemented are limited. For example schemes that
require an address decode to determine if a wait-state should be inserted are not possible
if operating at maximum frequency.
DMA access can be performed either by using the IRWAIT/DRWAIT signals to insert
wait states during a DMA access, or by using the dedicated DMA interface, which
avoids the need to externally multiplex critical interface signals when single cycle
access memory is used.
ARM DDI0198D
Copyright © 2001-2003 ARM Limited. All rights reserved.
5-3

Related parts for SAM9X35