SAM9XE256 Atmel Corporation, SAM9XE256 Datasheet - Page 125
SAM9XE256
Manufacturer Part Number
SAM9XE256
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE256
Flash (kbytes)
256 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 125 of 248
- Download datasheet (2Mb)
ARM DDI0198D
FORCE_NSEQ
DMAWAIT
DRADDR
REQCLK
DRWAIT
DRSEQ
DRRD
DRCS
SEQ
CLK
CS
RD
Figure 5-11 Cycle timing of circuit with DMA and single wait state for nonsequential accesses
A
T1
A
B
In cycle T1, the ARM926EJ-S initiates a sequential request to address A and the DMA
gains ownership of the TCM. DRWAIT is asserted because of DMAWAIT. The CS, A,
WE signals for the TCM are sourced from the DMA. The values of DRADDR,
DRBWL and DnRW are registered.
In cycle T2, the DMA access is still active (two cycle nonsequential access). DRWAIT
is held HIGH because of DMAWAIT.
In cycle T3, the DMA access completes and DMAWAIT is deasserted. The access
attributes captured at the end of T1 are used to generate the CS, A and WE signals for
the TCM. DRWAIT is asserted because of FORCE_NSEQ.
In cycle T4, FORCE_NSEQ is deasserted causing DRWAIT to be deasserted
indicating that the access will complete in the next cycle.
T2
Copyright © 2001-2003 ARM Limited. All rights reserved.
T3
A
D(B)
T4
T5
A+1
A+1
D(A)
D(A)
T6
D(A+1)
D(A+1)
A+2
A+2
T7
D(A+2)
D(A+2)
C
T8
Tightly-Coupled Memory Interface
T9
D
D
D(C)
T10
T11
D(D)
D(D)
5-17
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