AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 57
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AT32UC3C2512C Automotive
Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #2
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #3
- Current page: 57 of 225
- Download datasheet (4Mb)
12.2
12.2.1
7701E–AVR–02/11
Ports as General Digital I/O
Configuring the Pin
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 12-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
“EXT_CLOCK = external clock is selected as system clock.” on page
accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the
PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx register selects the direction of this pin. If DDxn is written logical
one, Pxn is configured as an output pin. If DDxn is written logical zero, Pxn is configured as an
input pin.
If PORTxn is written logical one when the pin is configured as an input pin, the pull-up resistor
is activated. To switch the pull-up resistor off, PORTxn has to be written logical zero or the pin
has to be configured as an output pin. The port pins are tri-stated when reset condition
becomes active, even if no clocks are running.
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
Atmel ATtiny24/44/84 [Preliminary]
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
SLEEP
(1)
SYNCHRONIZER
D
L
Q
Q
D
PINxn
Q
Q
RESET
RESET
PORTxn
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
PUD
WDx
RDx
RPx
clk
Figure 12-2
1
0
I/O
WRx
70, the DDxn bits are
WPx
shows a func-
I/O
,
57
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