ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 237

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

22.7.5
Table 22-7.
9223B–AVR–09/11
Status Code
Prescaler
(TWSR)
are 0
0xF8
0x00
Bits
Miscellaneous States
START or STOP condition
Bus error due to an illegal
Miscellaneous States
Serial Bus and 2-wire
information available;
Status of the 2-wire
No relevant state
Serial Interface
TWINT = “0”
Hardware
Figure 22-18. Formats and States in the Slave Transmitter Mode
There are two status codes that do not correspond to a defined TWI state, see
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format
frame. Examples of such illegal positions are during the serial transfer of an address byte, a
data byte, or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a
bus error, the TWSTO Flag must set and TWINT must be cleared by writing a logic one to it.
This causes the TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no
other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condi-
tion is transmitted.
Reception of the own
slave address and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
Atmel ATmega48PA/88PA/168PA [Preliminary]
No TWDR action
No TWDR action
To/from TWDR
From master to slave
From slave to master
Application Software Response
S
SLA
STA
0
STO
No TWCR action
1
R
DATA
To TWCR
TWINT
$A8
$B0
A
A
n
1
A
TWEA
DATA
X
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Next Action Taken by TWI Hardware
Wait or proceed current transfer
Only the internal hardware is affected,
no STOP condition is sent on the bus. In
all cases, the bus is released and
TWSTO is cleared.
$B8
A
DATA
$C0
$C8
A
A
Table
P or S
All 1's
22-7.
P or S
237