SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 32

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SAM3X8E

Manufacturer Part Number
SAM3X8E
Description
Manufacturer
Atmel Corporation
Datasheets
7.6
34
34
DMA Controller
SAM3X/A
SAM3X/A
Table 7-4.
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals below. The hardware interface numbers are also given in
7-5.
Table 7-5.
Instance Name
• Acting as one Matrix Master
• Embeds 4 (SAM3A and 100-pin SAM3X) or 6 (144-pin SAM3X) channels
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• Handles high speed transfer of SPI0-1, USART0-1, SSC and HSMCI (peripheral to memory,
• Memory to memory transfer
• Can be triggered by PWM and T/C which enables to generates waveform though the
32 bytes FIFO for Channel Buffering
8 bytes FIFO for Channel Buffering
memory to peripheral)
External Bus Interface
USART0
USART0
USART1
USART1
HSMCI
PWM
TWI0
TWI0
SPI0
SPI0
SPI1
SPI1
SSC
SSC
-
-
DMA Channel Size
DMA Channels
DMA Controller
Transmit/Receive
Channel T/R
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Receive
Receive
Receive
-
-
(Channels 0, 1 and 2)
100-pin SAM3X
(Channel 3)
DMA Channel HW
Interface Number
SAM3A
3
1
11
12
13
14
15
0
1
2
3
4
5
6
7
8
-
-
(Channels 0, 1, 2 and 4)
(Channels 3 and 5)
144-pin SAM3X
4
2
11057AS–ATARM–10-Feb-12
11057AS–ATARM–10-Feb-12
Table

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