AD9613 Analog Devices, AD9613 Datasheet - Page 26

• Manufacturer Part Number: AD9613
• Description: 12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9613

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 250MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9613
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 55. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,
AD9518, AD9520, AD9522, AD9523, and
offer excellent jitter performance.
CLOCK
CLOCK
Input Clock Divider
The AD9613 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. The
duty cycle stabilizer (DCS) is enabled by default on power-up.
The AD9613 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9613 contains a duty-cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9613.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The
duty cycle control loop does not function for clock rates less
than 40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 μs to 5 μs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the period that the
loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
INPUT
INPUT
50kΩ
Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
0.1µF
0.1µF
50kΩ
AD95xx
LVDS DRIVER
AD9524
100Ω
0.1µF
0.1µF
clock drivers
CLK+
CLK–
ADC
Rev. B | Page 26 of 36
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(f
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 56.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9613.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the
ADC System Performance, and the
Sample Systems and the Effects of Clock Phase Noise and Jitter,
for more information about jitter performance as it relates to
ADCs.
IN
) due to jitter (t
SNR
80
75
70
65
60
55
50
Figure 56. AD9613-250 SNR vs. Input Frequency and Jitter
1
HF
= −10 log[(2π × f
AN-501
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
J
) can be calculated by
Application Note, Aperture Uncertainty and
INPUT FREQUENCY (MHz)
10
IN
× t
JRMS
AN-756
)
2
+ 10
100
Application Note,
(
−
SNR
Data Sheet
LF
/
10
)
]
1000