AD7147A Analog Devices, AD7147A Datasheet - Page 32

• Manufacturer Part Number: AD7147A
• Manufacturer: Analog Devices

Specifications of AD7147A

• Resolution (bits): 16bit
• # Chan: 13
• Sample Rate: 111SPS
• Interface: I²C/Ser 2-Wire,Ser,SPI
• Analog Input Type: Capacitive
• Ain Range: ± 8 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

AD7147A
SERIAL INTERFACES
The AD7147A is available with an SPI interface. The AD7147A-1
is available with an I
same, with the exception of the serial interface.
SPI INTERFACE
The AD7147A has a 4-wire serial peripheral interface (SPI).
The SPI has a data input pin (SDI) for inputting data to the
device, a data output pin (SDO) for reading data back from the
device, and a data clock pin (SCLK) for clocking data into and
out of the device. A chip select pin ( CS ) enables or disables the
serial interface. CS is required for correct operation of the SPI.
Data is clocked out of the AD7147A on the negative edge of
SCLK and data is clocked into the device on the positive edge
of SCLK.
SPI Command Word
All data transactions on the SPI bus begin with the master
taking CS from high to low and sending out the command
word. This indicates to the AD7147A whether the transaction is
a read or a write and provides the address of the register from
which to begin the data transfer. The following bit map shows
the SPI command word.
MSB
15
1
SCLK
SDI
CS
14
1
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR THE CONTROL WORD AND 16 BITS FOR THE DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
CW
15
t
2
1
t
1
13
1
CW
ENABLE WORD
14
2
t
2
3
C-compatible interface. Both parts are the
CW
13
12
0
3
CW
12
4
11
0
CW
11
5
t
R/W
CW
4
10
10
R/W
6
16-BIT COMMAND WORD
CW
9
7
9:0
Register address
CW
8
8
Figure 48. Single Register Write SPI Timing
CW
7
t
5
9
REGISTER ADDRESS
CW
6
10
LSB
Rev. B | Page 32 of 68
CW
5
11
CW
4
12
CW
3
Bits[15:11] of the command word must be set to 11100 to
successfully begin a bus transaction.
Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates
a write.
Bits[9:0] contain the target register address. When reading or
writing to more than one register, this address indicates the
address of the first register to be written to or read from.
Writing Data
Data is written to the AD7147A in 16-bit words. The first word
written to the device is the command word, with the read/write
bit set to 0. The master then supplies the 16-bit input data-word
on the SDI line. The AD7147A clocks the data into the register
addressed in the command word. If there is more than one word of
data to be clocked in, the AD7147A automatically increments
the address pointer and clocks the subsequent data-word into
the next register.
The AD7147A continues to clock in data on the SDI line until
either the master finishes the write transition by pulling CS high
or the address pointer reaches its maximum value. The AD7147A
address pointer does not wrap around. When it reaches its
maximum value, any data provided by the master on the SDI
line is ignored by the AD7147A.
13
CW
2
14
CW
1
15
CW
0
16
D15
17
D14
18
D13
19
16-BIT DATA
D2
30
D1
t
8
31
D0
32