AD7294 Analog Devices, AD7294 Datasheet - Page 31

• Manufacturer Part Number: AD7294
• Description: 12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense
• Manufacturer: Analog Devices

Specifications of AD7294

• Resolution (bits): 12bit
• # Chan: 9
• Sample Rate: 200kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,2 V p-p,Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
CONFIGURATION REGISTER (0x09)
The configuration register is a 16-bit read/write register that
sets the operating modes of the AD7294. The bit functions of
the configuration register are outlined in Table 23 and Table 24.
On power-up, the configuration register is reset to 0x0000.
Sample Delay and Bit Trial Delay
It is recommended that no I
version is taking place; however, this may not be possible, for
example, when operating in autocycle mode. Bit D14 and Bit D13
in the configuration register are used to delay critical sample
intervals and bit trials from occurring while there is activity
on the I
Bit D13 (noise-delayed bit trials), and Bit D3 (I
enabled (set to 0). This configuration is appropriate for low
frequency applications because the bit trials are prevented from
occurring when there is activity on the I
Table 23. Configuration Register Bit Function Description D15 to D8
Channel
Bit
Function
Setting
Table 24. Configuration Register Bit Function Description D7 to D0
Channel
Bit
Function
Setting
Table 25. Alert/Busy Function Description
D2
0
0
1
1
Table 26. ADC Input Mode Example
D11
0
0
0
D1
0
1
0
1
2
C bus. On power-up, Bit D14 (noise-delayed sampling),
D15
Reserved
D7
2V
for V
Enabled = 1
Disabled = 0
ALERT/BUSY Pin Functions
Pin does not provide any interrupt signal.
Configures pin as a busy output.
Configures pin as an alert output.
Resets the ALERT/BUSY output pin, the alert_flag bit in the conversion result register, and the entire alert status register (if any is
active). 1,1 is written to Bits[D2:D1] in the configuration register to reset the ALERT/BUSY pin, the alert_flag bit, and the alert status
register. Following this write, the contents of the configuration register read 1, 0 for Bit D2 and Bit D1, respectively, if read back.
REF
IN
range
4
D10
0
0
1
D14
Noise-delayed
sampling. Use to
delay critical
sample intervals
from occurring
when there is
activity on the
I
Enabled = 0
Disabled = 1
2
C bus.
D6
2V
for V
Enabled = 1
Disabled = 0
2
C bus activity occur when a con-
REF
IN
range
3
2
D9
0
0
0
C bus, thus ensuring
D5
2V
for V
Enabled = 1
Disabled = 0
D13
Noise-delayed
bit trials. Use to
delay critical bit
trials from
occurring when
there is activity
on the I
Enabled = 0
Disabled = 1
2
C filters) are
REF
IN
range
2
2
C bus.
D8
0
1
1
D4
2V
for V
Enabled = 1
Disabled = 0
Rev. H | Page 31 of 48
REF
D12
Autocycle
mode
Enabled = 1
Disabled = 0
IN
range
1
good dc linearity perfor-mance. For high frequency input
signals, it may be desirable to have a known sampling point, thus
the noise-delayed sampling can be disabled by writing a 1 to Bit
D14 in the configuration register. This ensures that the
sampling instance is fixed relative to SDA, resulting in improved
SNR performance. If noise-delay samplings extend longer than 1
µs, the current conversion terminates. This termination can occur
if there are edges on SDA that are outside the I
When noise-delayed sampling is enabled, the rise and fall times
must meet the I
conversion time may vary.
The default configuration for Bit D3 (enabled) is recommended
for normal operation because it ensures that the I
for t
shorter than 50 ns. If this function is disabled, the conversion
results are more susceptible to noise from the I
D3
I
Enabled = 0
Disabled = 1
2
Description
All channels single-ended
Differential mode on V
Pseudo differential mode on V
C filters
Of
D11
Pseudo
differential
mode for
V
Enabled = 1
Disabled = 0
IN
(minimum)and t
3/V
IN
4
2
D2
ALERT pin
Enabled
D2 = 1
D1 = 0
Disabled
D2 = 0
C-specified standard. When D13 is enabled, the
D10
Pseudo
differential
mode for
V
Enabled = 1
Disabled = 0
IN
1/V
SP
IN
1/V
are met. The I
IN
2
IN
D1
BUSY pin (D2 = 0),
clear alerts (D2 = 1)
Enabled
D1 = 1 + D0 = 0
Disabled D1 = 0
2
IN
1/V
IN
D9
Differential
mode for
V
Enabled = 1
Disabled = 0
2
IN
3/V
2
C filters reject glitches
IN
4
2
C specification.
2
2
C requirements
C bus.
D0
Select ALERT
pin polarity
(active high/
active low)
Active high = 1
Active low = 0
D8
Differential
mode for
V
Enabled = 1
Disabled = 0
AD7294
IN
1/V
IN
2