AD7294 Analog Devices, AD7294 Datasheet - Page 39

• Manufacturer Part Number: AD7294
• Description: 12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense
• Manufacturer: Analog Devices

Specifications of AD7294

• Resolution (bits): 12bit
• # Chan: 9
• Sample Rate: 200kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,2 V p-p,Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
MODES OF OPERATION
There are two different methods of initiating a conversion on
the AD7294: command mode and autocycle mode.
COMMAND MODE
In command mode, the
either a single channel or a sequence of channels. To enter this
mode, the required combination of channels is written into the
command register (0x00). The first conversion takes place at the
end of this write operation, in time for the result to be read out
in the next read operation. While this result is being read out,
the next conversion in the sequence takes place, and so on.
To exit the command mode, the master should not acknowledge
the final byte of data. This stops the
allowing the master to assert a stop condition on the bus. It is
therefore important that, after writing to the command register,
a repeated start (Sr) signal be used rather than a stop (P) followed
by a start (S) when switching to read mode; otherwise, the
command mode exits after the first conversion.
After writing to the command register, the register pointer is
returned to its previous value. If a new pointer value is required
(typically the ADC Result Register 0x01), it can be written
immediately following the command byte. This extra write
operation does not affect the conversion sequence because the
second conversion triggers only at the start of the first read
operation.
The maximum throughput that can be achieved using this
mode with a 400 kHz I
Figure 56 shows the command mode converting on a sequence
of channels including V
1.
2.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
*
...
...
...
...
= POSITION OF A CONVERSION START
S
*
ALERT?
SLAVE ADDRESS
POINT TO RESULT REG (0x01)
V
V
IN
IN
2
0<7:0>
0<7:0>
C clock is (400 kHz/18) = 22.2 kSPS.
IN
AD7294
0, V
CH ID (100)
IN
1, and I
A
A
ADC converts on-demand on
*
0
AD7294
ALERT?
........
SENSE
A
I
SENSE
1.
transmitting,
CH ID (001)
POINT TO COMMAND REG (0x00)
1<11:8>
I
SENSE
A
SR
1<7:0>
Figure 56. Command Mode Operation
A
SLAVE ADDRESS
V
IN
Rev. H | Page 39 of 48
A
1<11:8>
I
SENSE
P
1<7:0>
A
3.
4.
5.
6.
7.
8.
9.
10. The master receives a data byte, which contains the
11. The master receives the second data byte, which contains
12. Point 10 and Point 11 repeat for Channel V
13. Once the master has received the results from all the
14. The master asserts a no acknowledge on SDA and a stop
The
occurs in a 5 ms period. To change the conversion sequence,
rewrite a new sequence to the command mode.
1
A
A
A
V
AD7294
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
*
The addressed slave device (AD7294) asserts an
acknowledge on SDA.
The master sends the Command Register Address 0x00.
The slave asserts an acknowledge on SDA.
The master sends the Data Byte 0x13 which selects the
V
The slave asserts an acknowledge on SDA.
The master sends the result register address (0x01). The
slave asserts an acknowledge on SDA.
The master sends the 7-bit slave address followed by the
write bit (high).
The slave (AD7294) asserts an acknowledge on SDA.
alert_flag bit, the channel ID bits, and the four MSBs of the
converted result for Channel V
an acknowledge on SDA.
the eight LSBs of the converted result for Channel V
The master then asserts on acknowledge on SDA.
Channel I
selected channels, the slave again converts and outputs
the result for the first channel in the selected sequence.
Point 10 to Point 12 are repeated.
condition on SDA to end the conversion and exit
command mode.
IN
ALERT?
*
IN
1<7:0>
ALERT?
0, V
COMMAND = 0x13
IN
automatically exits command mode if no read
1, and I
SENSE
CH ID (000)
A
CH ID (000)
1.
...
SENSE
1 channels.
*
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
A = ACKNOWLEDGE
A = NOT ACKNOWLEDGE
A
V
IN
V
IN
0<11:8>
0<11:8>
IN
0. The master then asserts
A
A
...
...
IN
1 and
AD7294
IN
0.