AD9222 Analog Devices, AD9222 Datasheet - Page 25

• Manufacturer Part Number: AD9222
• Description: Octal, 12-Bit, 40/50/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9222

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 65MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 68).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9222.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
A
) due only to aperture jitter (t
SNR Degradation = 20 × log 10(1/2 × π × f
130
120
100
110
90
80
70
60
50
40
30
1
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 68. Ideal SNR vs. Input Frequency and Jitter
AN-501
ANALOG INPUT FREQUENCY (MHz)
Application Note and the
10
0.125ps
0.25ps
J
0.5ps
1.0ps
2.0ps
) can be calculated by
100
AN-756
A
× t
16 BITS
14 BITS
12 BITS
J
)
1000
Rev. F | Page 25 of 60
Power Dissipation and Power-Down Mode
As shown in Figure 69, the power dissipated by the
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
500
450
400
350
300
250
200
150
100
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
50
Figure 69. Supply Current vs. f
0
Figure 70. Supply Current vs. f
0
10
10
AVDD CURRENT
15
AVDD CURRENT
20
DRVDD CURRENT
20
30
ENCODE (MSPS)
25
ENCODE (MSPS)
DRVDD CURRENT
TOTAL POWER
SAMPLE
SAMPLE
30
40
for f
for f
TOTAL POWER
35
IN
IN
= 10.3 MHz, AD9222- 50
= 10.3 MHz, AD9222- 65
50
40
45
60
AD9222
AD9222
50
950
900
850
800
750
700
0.800
0.750
0.700
0.650
0.600
0.550
0.500
is