AD7691 Analog Devices, AD7691 Datasheet - Page 18

• Manufacturer Part Number: AD7691
• Manufacturer: Analog Devices

Specifications of AD7691

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7691
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7691 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 35, and the corresponding timing is given in
Figure 36.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers, but CNV must be returned high before
the minimum conversion time elapses and then held high for
the maximum possible conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete,
the AD7691 enters the acquisition phase and powers down.
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling
ACQUISITION
SDI = 1
SDO
CNV
SCK
t
CNVH
Figure 36. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
CONVERSION
t
CONV
t
EN
D17
1
Rev. B | Page 18 of 28
t
HSDO
D16
2
t
CYC
ACQUISITION
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge can allow a faster reading rate, provided it has
an acceptable hold time. After the 18
when CNV goes high, whichever occurs first, SDO returns to
high impedance.
D15
t
3
ACQ
t
DSDO
t
VIO
SCKL
t
SCKH
Figure 35. 3-Wire CS Mode Without Busy Indicator
16
SDI
AD7691
t
SCK
CNV
SCK
Connection Diagram (SDI High)
17
D1
SDO
18
D0
t
DIS
th
SCK falling edge, or
CLK
CONVERT
DATA IN
DIGITAL HOST