AD7796 Analog Devices, AD7796 Datasheet - Page 12

• Manufacturer Part Number: AD7796
• Description: Low Power 16-Bit Sigma-Delta A/D Converter for Bridge Sensors
• Manufacturer: Analog Devices

Specifications of AD7796

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: ± (Vref/128)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7796/AD7797
STATUS REGISTER
RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communication register,
select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status
register. SR0 through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the
data stream. The number in brackets indicates the power-on/reset default status of that bit.
MSB
SR7
RDY(1)
Table 11. Status Register Bit Designations
Bit Location
SR7
SR6
SR5 to SR3
SR2 to SR0
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A
The mode register is a 16-bit read/write register. This register is used to select the operating mode, update rate, and clock source. Table 12
outlines the bit designations for this register. MR0 through MR15 indicate the bit locations, with MR denoting that the bits are in the
mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that
bit. Any write to the setup register resets the modulator and filter, and sets the RDY bit.
MSB
MR15
MD2(0)
Table 12. Mode Register Bit Designations
Bit Location
MR15 to MR13
MR12 to MR8
MR7 to MR6
MR5 to MR4
MR3 to MR0
MR14
MD1(0)
Bit Name
RDY
ERR
0
CH2 to CH0
Bit Name
MD2 to MD0
0
CLK1 to CLK0
0
FS3 to FS0
SR6
ERR(0)
MR13
MD0(0)
MR12
0(0)
Description
Ready Bit for ADC. Cleared when data is written to the ADC data register. Set automatically after the ADC data
register has been read or before the data register is updated with a new conversion result to indicate to the
user not to read the conversion data. It is also set when the part is placed in power-down mode. DOUT/RDY
also indicates the end of a conversion and can be used as an alternative to the status register for monitoring
the ADC for conversion data.
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the
ADC data register has been clamped to all 0s or all 1s. Error sources include overrange and underrange.
Cleared by a write operation to start a conversion.
These bits are automatically cleared.
These bits indicate the channel that is being converted by the ADC.
Description
Mode Select Bits. These bits select the operational mode of the AD7796/AD7797 (see Table 13).
These bits must be programmed with a Logic 0 for correct operation.
These bits are used to select the clock source for the AD7796/AD7797. Either an on-chip 64 kHz clock
or an external clock can be used. The ability to override using an external clock allows several AD7796/
AD7797 devices to be synchronized. In addition, 50 Hz/60 Hz rejection is improved when an accurate
external clock drives the AD7796/AD7797.
CLK1
0
0
1
1
These bits must be programmed with a Logic 0 for correct operation.
Filter Update Rate Select Bits (see Table 14).
SR5
0(0)
MR11
0(0)
CLK0
0
1
0
1
MR10
0(0)
ADC Clock Source
Internal 64 kHz Clock. Internal clock is not available at the CLK pin.
Internal 64 kHz Clock. This clock is made available at the CLK pin.
External 64 kHz Clock Used. An external clock gives better 50 Hz/60 Hz rejection.
See Table 1 for the external clock specifications.
External Clock Used. The external clock is divided by 2 within the AD7796/AD7797.
SR4
0(0)
MR9
0(0)
Rev. A | Page 12 of 24
MR8
0(0)
SR3
0(0)
MR7
CLK1(0)
MR6
CLK0(0)
SR2
CH2(0)
MR5
0(0)
MR4
0(0)
SR1
CH1(0)
MR3
FS3(1)
MR2
FS2(0)
LSB
SR0
CH0(0)
MR1
FS1(1)
LSB
MR0
FS0(0)