AD7829-1 Analog Devices, AD7829-1 Datasheet - Page 15

• Manufacturer Part Number: AD7829-1
• Description: 3 V/5 V, 2 MSPS, 8-Bit, 8-Channel ADC
• Manufacturer: Analog Devices

Specifications of AD7829-1

• Resolution (bits): 8bit
• # Chan: 8
• Sample Rate: 2MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: 2 V p-p,2.5V p-p,Uni 2.0V,Uni 2.5V
• Adc Architecture: Flash
• Pkg Type: SOIC,SOP

Figure 19 shows the power vs. throughput rate for automatic,
full power-down.
100
0.1
10
–10
–20
–30
–40
–50
–60
–70
–80
1
0
DB0 TO DB7
0
0
CONVST
50
Figure 19. AD7829-1 Power vs. Throughput
EOC
CS
RD
100
TRACK
150
Figure 20. AD7829-1 SNR
THROUGHPUT (kSPS)
200
FREQUENCY (kHz)
t
2
250
120ns
HOLD
300
350
2048 POINT FFT
SAMPLING
2MSPS
f
IN
400
= 200kHz
t
1
450
5
0
0
Figure 21. Mode 1 Operation
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OPERATING MODES
The AD7829-1 has two possible modes of operation, depending
on the state of the CONVST pulse approximately 100 ns after the
end of a conversion, that is, upon the rising edge of the
Mode 1 Operation (High-Speed Sampling)
When the AD7829-1 is operated in Mode 1, it is not powered
down between conversions. This mode of operation allows high
throughput rates to be achieved. Figure 21 shows how this
optimum throughput rate is achieved by bringing CONVST
high before the end of a conversion, that is, before the EOC
pulses low. When operating in this mode, a new conversion
should not be initiated until 30 ns after the end of a read
operation. This allows the track/hold to acquire the analog
signal to 0.5 LSB accuracy.
Mode 2 Operation (Automatic Power-Down)
When the AD7829-1 is operated in Mode 2 (see Figure 22), it
automatically powers down at the end of a conversion. The
CONVST signal is brought low to initiate a conversion and is
left logic low until after the EOC goes high, that is, approximately
100 ns after the end of the conversion. The state of the CONVST
signal is sampled at this point (that is, 530 ns maximum after
CONVST falling edge) and the AD7829-1 powers down as long
as CONVST is low. The ADC is powered up again on the rising
edge of the CONVST signal. Superior power performance can
be achieved in this mode of operation by powering up the
AD7829-1 only to carry out a conversion. The parallel interface
of the AD7829-1 is still fully operational while the ADCs are
powered down. A read can occur while the part is powered
down, and so it does not necessarily need to be placed within
the
EOC pulse, as shown in Figure 22.
TRACK
VALID
DATA
t
3
HOLD
AD7829-1
EOC pulse.