AD7658 Analog Devices, AD7658 Datasheet - Page 24
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AD7658
Manufacturer Part Number
AD7658
Description
250 kSPS, 6-Channel,SimultaneousSampling, Bipolar 12-Bit A/D Converter
Manufacturer
Analog Devices
Datasheet
1.AD7656.pdf
(32 pages)
Specifications of AD7658
Resolution (bits)
12bit
# Chan
6
Sample Rate
250kSPS
Interface
Par,Ser,SPI
Analog Input Type
SE-Bip
Ain Range
Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 5.0V
Adc Architecture
SAR
Pkg Type
QFP
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AD7656/AD7657/AD7658
Software Selection of ADCs
The H /S SEL pin determines the source of the combination of
ADCs that are to be simultaneously sampled. When the H /S SEL
pin is logic low, the combination of channels to be simultaneously
sampled is determined by the CONVST A, CONVST B, and
CONVST C pins. When the H /S SEL pin is logic high, the
combination of channels selected for simultaneous sampling is
determined by the contents of the Control Register DB15 to
Control Register DB13. In this mode, a write to the control
register is necessary.
The control register is an 8-bit write-only register. Data is written
to this register using the CS and WR pins and the DB[15:8] data
pins (see
To select an ADC pair to be simultaneously sampled, set the
corresponding data line high during the write operation.
The AD7656/AD7657/AD7658 control register allows
individual ranges to be programmed on each ADC pair.
DB12 to DB10 in the control register are used to program
the range on each ADC pair.
After a reset occurs on the AD7656/AD7657/AD7658, the
control register contains all zeros.
The CONVST A signal is used to initiate a simultaneous
conversion on the combination of channels selected via the
control register. The CONVST B and CONVST C signals can
be tied low when operating in software mode ( H /S SEL = 1).
The number of read pulses required depends on the number
of ADCs selected in the control register and on whether the
devices are operating in word or byte mode. The conversion
results are output in ascending order.
During the write operation, Data Bus Bit DB15 to Bit DB8 are
bidirectional and become inputs to the control register when
RD is logic high and CS and WR are logic low. The logic state
on DB15 through DB8 is latched into the control register when
WR goes logic high.
Table 10. Control Register Bit Function Descriptions
(Default All 0s)
DB15
VC
DB14
VB
Figure 29
DB13
VA
). The control register is shown in
DB12
RNGC
DB11
RNGB
DB15 TO DB8
DB10
RNGA
Figure 29. Parallel Interface—Write Cycle for Word Mode ( W /B= 0)
WR
CS
DB9
REFEN
Table 10
t
12
DB8
REFBUF
Rev. C | Page 24 of 32
.
t
11
t
DATA
14
Table 11.
Bit
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
t
15
t
13
Mnemonic
VC
VB
VA
RNGC
RNGB
RNGA
REFEN
REFBUF
Comment
This bit is used to select Analog Inputs V5
and V6 for the next conversion.
When this bit = 1, V5 and V6 are
simultaneously converted on the
next CONVST A rising edge.
This bit is used to select Analog Inputs
V3 and V4 for the next conversion.
When this bit = 1, V3 and V4 are
simultaneously converted on the
next CONVST A rising edge.
This bit is used to select Analog Inputs
V1 and V2 for the next conversion.
When this bit = 1, V1 and V2 are
simultaneously converted on the
next CONVST A rising edge.
This bit is used to select the analog input
range for Analog Inputs V5 and V6.
When this bit = 1, the ±2 × V
selected for the next conversion.
When this bit = 0, the ±4 × V
selected for the next conversion.
This bit is used to select the analog input
range for Analog Inputs V3 and V4.
When this bit = 1, the ±2 × V
selected for the next conversion.
When this bit = 0, the ±4 × V
selected for the next conversion.
This bit is used to select the analog input
range for Analog Inputs V1 and V2.
When this bit = 1, the ±2 × V
selected for the next conversion.
When this bit = 0, the ±4 × V
selected for the next conversion.
This bit is used to select the internal
reference or an external reference.
When this bit = 0, the external reference
mode is selected. When this bit = 1, the
internal reference is selected.
This bit is used to select between using the
internal reference buffers and choosing
to bypass these reference buffers.
When this bit = 0, the internal reference
buffers are enabled and decoupling is
required on the REFCAP pins. When this
bit = 1, the internal reference buffers are
disabled and a buffered reference should
be applied to the REFCAP pins.
REF
REF
REF
REF
REF
REF
mode is
mode is
mode is
mode is
mode is
mode is