AD7746 Analog Devices, AD7746 Datasheet - Page 12

• Manufacturer Part Number: AD7746
• Description: 24-bit, 2 Channel Capacitance to Digital Converter
• Manufacturer: Analog Devices

Specifications of AD7746

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: n/a
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,± 4 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7745/AD7746
SERIAL INTERFACE
The AD7745/AD7746 supports an I
interface. The two wires on the I
and SDA (data). These two wires carry all addressing, control,
and data information one bit at a time over the bus to all
connected peripheral devices. The SDA wire carries the data,
while the SCL wire synchronizes the sender and receiver during
the data transfer. I
slave devices. A device that initiates a data transfer message is
called a master, while a device that responds to this message is
called a slave.
To control the AD7745/AD7746 device on the bus, the
following protocol must be followed. First, the master initiates a
data transfer by establishing a start condition, defined by a
high-to-low transition on SDA while SCL remains high. This
indicates that the start byte follows. This 8-bit start byte is made
up of a 7-bit address plus an R/W bit indicator.
All peripherals connected to the bus respond to the start
condition and shift in the next 8 bits (7-bit address + R/W bit).
The bits arrive MSB first. The peripheral that recognizes the
transmitted address responds by pulling the data line low
during the ninth clock pulse. This is known as the acknowledge
bit. All other devices withdraw from the bus at this point and
maintain an idle condition. An exception to this is the general
call address, which is described later in this document. The idle
condition is where the device monitors the SDA and SCL lines
waiting for the start condition and the correct address byte. The
R/W bit determines the direction of the data transfer. A Logic 0
LSB in the start byte means that the master writes information
to the addressed peripheral. In this case the AD7745/AD7746
becomes a slave receiver. A Logic 1 LSB in the start byte means
that the master reads information from the addressed peri-
pheral. In this case, the AD7745/AD7746 becomes a slave
transmitter. In all instances, the AD7745/AD7746 acts as a
standard slave device on the I
The start byte address for the AD7745/AD7746 is 0x90 for a
write and 0x91 for a read.
READ OPERATION
When a read is selected in the start byte, the register that is
currently addressed by the address pointer is transmitted on to
the SDA line by the AD7745/AD7746. This is then clocked out
by the master device and the AD7745/AD7746 awaits an
acknowledge from the master.
If an acknowledge is received from the master, the address auto-
incrementer automatically increments the address pointer
register and outputs the next addressed register content on to
the SDA line for transmission to the master. If no acknowledge
is received, the AD7745/AD7746 return to the idle state and the
address pointer is not incremented.
2
C devices are classified as either master or
2
C bus.
2
C bus are called SCL (clock)
2
C-compatible 2-wire serial
Rev. 0 | Page 12 of 28
The address pointers’ auto-incrementer allow block data to be
written or read from the starting address and subsequent
incremental addresses.
In continuous conversion mode, the address pointers’ auto-
incrementer should be used for reading a conversion result.
That means, the three data bytes should be read using one
multibyte read transaction rather than three separate single byte
transactions. The single byte data read transaction may result in
the data bytes from two different results being mixed. The same
applies for six data bytes if both the capacitive and the
voltage/temperature channel are enabled.
The user can also access any unique register (address) on a one-
to-one basis without having to update all the registers. The
address pointer register contents cannot be read.
If an incorrect address pointer location is accessed or, if the user
allows the auto-incrementer to exceed the required register
address, the following applies:
•
•
WRITE OPERATION
When a write is selected, the byte following the start byte is
always the register address pointer (subaddress) byte, which
points to one of the internal registers on the AD7745/ AD7746.
The address pointer byte is automatically loaded into the
address pointer register and acknowledged by the AD7745/
AD7746. After the address pointer byte acknowledge, a stop
condition, a repeated start condition, or another data byte can
follow from the master.
A stop condition is defined by a low-to-high transition on SDA
while SCL remains high. If a stop condition is ever encountered
by the AD7745/AD7746, it returns to its idle condition and the
address pointer is reset to Address 0x00.
If a data byte is transmitted after the register address pointer
byte, the AD7745/AD7746 load this byte into the register that is
currently addressed by the address pointer register, send an
acknowledge, and the address pointer auto-incrementer auto-
matically increments the address pointer register to the next
internal register address. Thus, subsequent transmitted data
bytes are loaded into sequentially incremented addresses.
In read mode, the AD7745/AD7746 continues to output
various internal register contents until the master device
issues a no acknowledge, start, or stop condition. The
address pointers’ auto-incrementer’s contents are reset to
point to the status register at Address 0x00 when a stop
condition is received at the end of a read operation. This
allows the status register to be read (polled) continually
without having to constantly write to the address pointer.
In write mode, the data for the invalid address is not loaded
into the AD7745/AD7746 registers but an acknowledge is
issued by the AD7745/AD7746.