AD7685 Analog Devices, AD7685 Datasheet - Page 18

• Manufacturer Part Number: AD7685
• Manufacturer: Analog Devices

Specifications of AD7685

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7685
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7685 is connected
to an SPI-compatible digital host.
The connection diagram is shown in Figure 34, and the
corresponding timing is given in Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When conversion is completed, the AD7685
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges. The data is
SDI = 1
ACQUISITION
CNV
SCK
SDO
t
CNVH
CONVERSION
Figure 35. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
t
CONV
t
EN
D15
1
Rev. C | Page 18 of 28
t
HSDO
D14
2
t
CYC
ACQUISITION
D13
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge will
allow a faster reading rate provided it has an acceptable hold
time. After the 16th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
t
3
ACQ
t
DSDO
t
VIO
SCKL
t
SCKH
14
SDI
Figure 34. CS Mode 3-Wire, No BUSY Indicator
AD7685
t
SCK
CNV
SCK
15
Connection Diagram (SDI High)
D1
SDO
16
D0
t
DIS
CONVERT
DATA IN
CLK
DIGITAL HOST