AD9861 Analog Devices, AD9861 Datasheet
AD9861
Specifications of AD9861
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AD9861 Summary of contents
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... AD9861 is optimized for high performance, low power, small form factor, and to provide a cost-effective solution for the broadband communication market. The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADC and TxDAC clocks are generated within a timing generation block that provides user programma- ble options such as divide circuits, PLL multipliers, and switches ...
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... AD9861 TABLE OF CONTENTS Tx Path Specifications...................................................................... 3 Rx Path Specifications...................................................................... 4 Power Specifications......................................................................... 5 Digital Specifications........................................................................ 5 Timing Specifications....................................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Pin Function Descriptions...................... 8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 21 REVISION HISTORY Revision 0: Initial Version Theory of Operation ...................................................................... 22 System Block ............................................................................... 22 Rx Path Block.............................................................................. 22 Tx Path Block ...
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... Tx PATH SPECIFICATIONS Table 1. AD9861-50 and AD9861- 200 MSPS; 4× interpolation; R DAC SET unless otherwise noted Parameter Tx PATH GENERAL Resolution Maximum DAC Update Rate Maximum Full-Scale Output Current Full-Scale Error Gain Mismatch Error Offset Mismatch Error Reference Voltage Output Capacitance Phase Noise (1 kHz Offset, 6 MHz Tone) ...
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... AD9861 Rx PATH SPECIFICATIONS Table 2. AD9861-50 and AD9861- MSPS for the AD9861-50, 80 MSPS for the AD9861-80; internal reference; differential analog inputs, ADC ADC_AVDD = DVDD = 3.3V, unless otherwise noted Parameter Rx PATH GENERAL Resolution Maximum ADC Sample Rate Gain Mismatch Error Offset Mismatch Error Reference Voltage Reference Voltage (REFT– ...
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... POWER SPECIFICATIONS Table 3. AD9861-50 and AD9861-80 Analog and digital supplies = 3 Parameter POWER SUPPLY RANGE Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Driver Supply Voltage (DRVDD) ANALOG SUPPLY CURRENTS TxPath (20 mA Full-Scale Outputs) TxPath (2 mA Full-Scale Outputs) Rx Path (-80 MSPS) ...
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... AD9861 TIMING SPECIFICATIONS Table 5. AD9861-50 and AD9861-80 Parameter INPUT CLOCK CLKIN Clock Rate (PLL Bypassed) PLL Input Frequency PLL Ouput Frequency TxPATH DATA Setup Time (HD20 Mode, Time Required Before Data Latching Edge) Hold Time (HD20 Mode, Time Required After Data Latching Edge) Latency 1× ...
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... LPM Air) 3.9 V max JA θ = 30.8 (paddle not soldered to ground plan, 0 LPM Air) 3.9 V max JA –0 AVDD + 0.3 V –0 DVDD – 0 max –40°C to +85°C 150°C 300°C –65°C to +150°C Rev Page AD9861 ...
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... IFACE2 (10/20) 18 IFACE3 19–28 U9–U0 29 AUX1 30 AUX2 33 IFACE1 SPI_DIO 1 SPI_CLK DVDD 5 DVSS 6 AD9861 AVDD 7 TOP VIEW IOUT–A 8 (Not to Scale) IOUT+A 9 AGND 10 REFIO 11 FSADJ 12 AGND 13 IOUT+B 14 IOUT–B 15 AVDD Figure 3 ...
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... Underlined pin names and descriptions apply when the device is configured without a serial port interface, referred SPI mode. 2 Pin function depends if the serial port is used to configure the AD9861 (called SPI mode mode pins are used to configure the AD9861 (called No SPI mode). The differences are indicated by the SPI and No SPI labels in the description column. ...
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... Figure 7. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 Figure 8. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 Figure 9. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Rev ...
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... Figure 13. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Figure 14. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone –50 –55 –60 –65 –70 –75 – Figure 15. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone Rev Page ...
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... Figure 19. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone THD and SFDR Performance vs. Input Amplitude AVE (–40°C) AVE (+25°C) AVE (+85°C) 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V) Figure 20. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SINAD Performance vs. ADC_AVDD and Temperature AVE (+85° AVE (+25°C) 75 AVE (– ...
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... Figure 25. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 Figure 26. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 Figure 27 ...
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... LOW POWER ADC @ 40MSPS –70 –75 ULTRALOW POWER NORMAL POWER @ 80MSPS – INPUT FREQUENCY (MHz) Figure 32. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone THD Performance vs. Input Frequency and Power Setting SFDR THD 0 –5 –10 –15 –20 –25 –30 INPUT AMPLITUDE (dBFS) Figure 33 ...
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... Figure 37. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone 2.7 3.6 Figure 38. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone 180 NORM 160 140 120 100 Figure 39. AD9861-80 ADC_AVDD Current vs. ADC Sampling Rate for Rev Page AVE (+85° ...
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... Figure 44. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 60 Ω Differential Load 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 Figure 45 ...
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... Full-Scale Output into 600 Ω Differential Load Figure 50. AD9861 Tx Path SINAD vs. Output Frequency of Tx Path, with 2 mA Full-Scale Output into 600 Ω Differential Load –70 –75 –80 –85 –90 – Figure 51. AD9861 Tx Path Dual-Tone (0.5 MHz Spacing) IMD vs. ...
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... FREQUENCY (MHz) Figure 55. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 52 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 FREQUENCY (MHz) Figure 56. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure FREQUENCY (MHz) Figure 57. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 4× Interpolation 21.25 31.5 32.0 32 ...
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... Figure 59. AD9861 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 58 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) Figure 60. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 1× Interpolation –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 7.4 7.6 7.8 8.0 –40 – ...
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... FREQUENCY (MHz) Figure 68. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 64 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) Figure 69. AD9861 Tx Path FFT of OFDM Signal in Figure 52 with 4× Interpolation 23.3 23.4 35.1 35.3 35 ...
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... SFDR does not include harmonic distortion components. ⎞ Z ⎟ Worst Other Spur INPUT ⎟ ⎠ The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dBc. Rev Page AD9861 ...
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... Rx PATH BLOCK Rx Path General Description The AD9861 Rx path consists of two 10-bit, 50 MSPS (for the AD9861-50 MSPS (for the AD9861-80) analog-to-digital converters (ADCs). The dual ADC paths share the same clocking and reference circuitry to provide optimal matching characteristics ...
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... In systems that must use dc coupling, use an op amp to comply with the input requirements of the AD9861. The inputs accept a signal with p-p differential input swing centered about one-half of the supply voltage (AVDD/2). If the dc bias is supplied exter- ...
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... Register 0x0A (MSB) ‘0111 0000’ Either of the ADCs in the AD9861 Rx path can be placed in standby mode independently by writing to the appropriate SPI register bits in Registers 3, 4, and 5. The minimum standby power is achieved when both channels are placed in full power- ...
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... LO leakage signal that typically results at the output of the modulator. If the AD9861 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the AD9861 as well as the input offset on the modulator. The reference circuitry is shown in Figure 74. 0.1µF Referring to the transfer function of the following equation, ...
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... The quality of the clock and data input signals is important in achieving optimum performance. The external clock driver circuitry provides the AD9861 with a low jitter clock input that meets the min/max logic levels while providing fast edges. When a driver is used to buffer the clock input, it should be ...
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... Pin 46 can be connected to AuxDAC_C and/or AuxADC_B. Auxiliary DACs The AD9861 integrates three 8-bit voltage output auxiliary digital-to-analog converters (AuxDACs), which can be used for supplying various control voltages throughout the system such as a VCXO voltage control or external VGA gain control. The ...
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... MHz. Operation of the Aux_SPI requires that 3-wire SPI mode be used, disabling the SDO pin. If the controller is a 4-wire interface, a method of connecting the 3-wire AD9861 interface to the 4-wire controller is suggested in Figure 75. An example of an AuxSPI access is shown in Figure 75. In the AuxSPI configuration, a start convert is initiated by applying a rising edge to the Aux_SPI_CS pin ...
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... Figure 77. AuxADC Data Cycle Times for Various Readout Methods Rev Page 03606-0-021 16 SPI CLK 16 SPI CLKs USED TO READ BACK 8 REGISTER BITS 16 SPI CLKs USED TO READ BACK 8 REGISTER BITS 8-BIT SERIAL OUTPUT SPI CLK SPI CLK C 03606-0-007 AD9861 ...
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... AD9861 DIGITAL BLOCK The AD9861 digital block allows the device to be configured in various timing and operation modes. The following sections discuss the flexible I/O interfaces, the clock distribution block, and the programming of the device through mode pins or SPI registers. Table 11. Flexible Data Interface Modes ...
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... Table 12 describes AD9861 pin function (when mode pins are used) relative to I/O mode, and for half-duplex modes whether transmitting or receiving. Table 12. AD9861 Pin Function vs. Interface Mode (No SPI Cases) Mode Name U10 FD Interleaved Tx Data HD10 Interleaved Tx Data (Tx High) HD10 MSB = RxSYNC (Tx Low) ...
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... Rx and Tx synchronization pins (RxSYNC and TxSYNC). Both the U10 and L10 buses are used on the AD9861, but the logic level of the Tx/ Rx selector (controlled through IFACE1 pin) is used to disable and three-state the unused bus, allowing U10 and L10 to be tied together ...
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... The flexible interface can be configured with or without the SPI, although more options and flexibility are available when using the SPI to program the AD9861. Mode pins can be used to power down sections of the device, reduce overall power consump- tion, configure the flexible I/O interface, and program the interpolation setting ...
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... AD9861 Table 15. Mode Pin Names and Descriptions Pin Name Description ADC_LO_PWR ADC Low Power Mode Option. ADC_LO_PWR is latched during the rising edge of RESET. Logic low results in ADC operation at nominal power mode. Logic high results in ADC consuming 40% less power than the nominal power mode. ...
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... The flexible interface can be configured with register settings. Using the register allows more device programmability. Table 16 shows the required register writes to configure the AD9861 for FD, optional FD, HD20, optional HD20, HD10, optional HD10, and clone mode. Note that for modes that use interleaved data buses, enabling 2× or 4× interpolation is required. ...
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... AD9861 SPI Register Map Registers 0x00 to 0x29 of the AD9861 provide flexible operation of the device. The SPI allows access to many configurable options. Detailed descriptions of the bit functions are found in Table 18. Table 17. Register Map Reg. Name Addr 7 6 General 0x00 SDIO BiDir LSB First ...
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... Setting this register bit high forces the CLKIN multiplier to a power-down state. This mode can be used to conserve power or to bypass the internal PLL. To operate the AD9861 when the PLL is bypassed, an external clock equal to the fastest on-chip clock is supplied to the CLKIN. ...
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... AD9861 Register Bit Bit 6: RxREF (Power-Down) Bit 5: DiffRef (Power-Down) Bit 4: VREF (Power-Down) Registers 6/7: Rx Path Bit 5: Rx_A Twos Complement/ Rx_B Twos Complement Bit 4: Rx_A Clk Duty/Rx_B Clk Duty Registers 8/9/A: Rx Path Rx Ultralow Power Control Bits Registers 0B/0C/0E/0F: Tx Path DAC A/DAC B Offset DAC A/DAC B Offset Direction ...
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... Setting this bit high switches the IFACE2 output signal to the PLL output clock valid only if Register 0x01, Bit 2 is enabled or if full-duplex mode is configured. Changes the PLL loop bandwidth and changes the profile of the phase noise generated from the PLL clock. Rev Page AD9861 ...
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... These 10-bit, offset binary registers are read-only and store the last corresponding AuxADC output values. The AD9861 has two AuxADC SAR converters: AuxADC A and AuxADC B. AuxADC A has a multiplexed input, which allows the user to select either input by using the Select A register. The 10 bits are broken into two registers, one containing the upper eight bits and the other containing the lower two bits ...
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... Setting any of these bits high synchronizes AuxDAC updates only when the TxPwrDwn rising edge occurs. This syncronizes the AuxDAC update to the Tx path power-up. Setting any of these bits high powers up the appropriate AuxDAC. By default, these bits are low and the AuxDACs are disabled. Rev Page AD9861 ...
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... An example of this is to write the AD9861 power-down bits. All data input to the AD9861 is registered on the rising edge of SCLK. All data is driven out of the AD9861 on the falling edge of SCLK. Instruction Byte The instruction byte contains the information shown in Table 19, and the bits are described in detail after the table ...
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... DON'T CARE REGISTER DATA REGISTER (N–1) DATA REGISTER (N+1) DATA AD9861 DON'T CARE 03606-0-022 DON'T CARE DON'T CARE 03606-0-023 DON'T CARE DON'T CARE 03606-0-024 ...
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... AD9861 Read Operation The readback of registers can be a single or dual data byte operation. The readback can be configured to use 3-wire or 4-wire and can be formatted with MSB first or LSB first. The instruction header is written to the device either MSB or LSB first (depending on the mode) followed by the 8-bit output data (appropriately MSB or LSB justified) ...
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... CLOCK DISTRIBUTION BLOCK Theory/Description The AD9861 uses a clock distribution block to distribute the timing derived from the input clock (applied to the CLKIN pin, referred to here as CLKIN) to the Rx and Tx paths. There are many options for configuring the clock distribution block, which are available through internal register settings. The Clock ...
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... IFACE2 pin can be used to invert the IFACE2 output. Configuration The AD9861 timing for the transmit path and for the receive path depend on the mode setting and various programmable options. The registers that affect the output clock timing and data input/output timing are clk_mode [2:0] ...
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... IFACE3 (CLKOUT) Tx DATA Figure 85. Tx Data Timing Diagram Table 24 shows typical setup-and-hold times for the AD9861 in the various mode configurations. Function 0: There is no clock output from IFACE2 pin, except in FD mode. 1: The IFACE2 pin outputs a continuous reference clock from the PLL output mode, this inverts the IFACE2 output ...
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... Configuration without Serial Port Interface (Using Mode Pins) The AD9861 can be configured using mode pins if a serial port interface is not available. This section applies only to configuring the AD9861 without an SPI. Refer is the Digital Block, Configuring with Mode Pins section for further information. ...
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... TOP 8.75 VIEW BSC SQ 0.45 0. 0.35 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION Figure 87. 64-Lead Lead Frame Chip Scale Package (LFCSP) [CP-64] Rev Page 0.30 0.25 0.60 MAX 0.18 PIN 1 INDICATOR 64 1 7.25 BOTTOM 7.10 SQ* VIEW 6. 0.25 MIN 7.50 REF AD9861 ...
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... Temperature Range AD9861BCP-50 –40°C to +85°C (Ambient) AD9861BCP-80 –40°C to +85°C (Ambient) AD9861BCPRL-50 –40°C to +85°C (Ambient) AD9861BCPRL-80 –40°C to +85°C (Ambient) AD9861-50EB 25°C (Ambient) AD9861-80EB 25°C (Ambient) Package Description 64-Lead LFCSP 64-Lead LFCSP 64-Lead LFCSP 64-Lead LFCSP ...
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... NOTES Rev Page AD9861 ...
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... AD9861 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03606–0–11/03(0) Rev Page ...