AD9861 Analog Devices, AD9861 Datasheet - Page 28

• Manufacturer Part Number: AD9861
• Manufacturer: Analog Devices

Specifications of AD9861

• Resolution (bits): 10bit
• # Chan: 2
• Sample Rate: 80MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9861
Table 10. Configuring AuxADC Reference
AuxADC_A Reference
Configuration
Buffered PLL_VDD
Internal 3.0 V (3 x VREF)
Internal 2.5 V (2.5 x VREF)
Externally forced
The AuxADCs can convert at rates of up to 5.33 MSPS
(0.1875 µs maximum conversion time) and have a bandwidth
of around 200 kHz. The conversion time, including setup,
requires 12 clock cycles. The maximum clock rate for the
AuxADCs is 64 MHz and is generated from a divided down Rx
ADC clock. The divide down ratio is controlled by register
AuxADC Clock Div [Register 0x23, Bits 1, 0]. By default, the Rx
ADC clock is divided by 4. At an Rx ADC rate greater than 64
MHz, the AuxADC Clock Div register must be set to divide-by-
2 or divide-by-4.
On-chip averaging of 2, 4, 8, 16, 32, or 64 samples can be
enabled through Register 0x18 for AuxADC_A or through
Register 0x19 for AuxADC_B. When the averaging option is
enabled, the AuxADC continually converts the number of
samples specified and outputs the average value.
There are three modes of operating the AuxADC: SPI operation
mode (default), SPI with external start convert operation mode,
and Aux_SPI operation mode.
In the default SPI operation mode, a conversion is initiated by
writing a logic high to one or both of the start register bits,
Start A or Start B [Register 0x22, Bit 0 or Bit 3]. If AuxADC is
configured as averaging mode, the proper start bit is the Start
Average AuxADC A/B register [Register 0x18, Bit 7/Register
0x19, Bit 7].
When the conversion is complete, the straight binary, 10-bit
output data of the AuxADC is written to one of three reserved
locations in the register map, depending on which AuxADC
and which multiplexed input is selected. Because the AuxADCs
output 10 bits, two register addresses are needed for each data
location.
In the optional SPI with external start convert operation mode,
the conversion is initiated by asserting AuxSPI_csb, and data
retrieval is accomplished through the SPI interface (data
retrieval is similar to the default operation). The AuxSPI_csb
can be configured to initiate the conversion of either one of the
AuxADCs. This mode is configured by setting the AuxSPI
enable register bit [Register 0x22, Bit 7].
An optional auxiliary serial port interface (AuxSPI) can be used
to access an AuxADC. The AuxSPI can initiate an AuxADC
conversion and can be used to retrieve the data. The AuxSPI
can be configured to allow dedicated control of one of the
AuxADC Ref Enable
[Register 0x17, Bit 1]
0
1
1
0
AuxADC Ref FS
[Register 0x17, Bit 0]
0
0
1
Don't Care
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AuxADCs and is available so that the SPI is not continually
busy retrieving AuxADC data.
The AuxSPI can be enabled and configured by setting register
AuxSPI enable [Register 0x22, Bit 7]. Also required is that the
normal serial port interface be configured for 3-wire mode (the
SPI_SDO pin must be disabled to use the Aux_SPI_SDO pin)
by setting the SDIO BiDir register bit [Register 0x00, Bit 7].
Register bit Sel BnotA [Register 0x22, Bit 6] configures whether
AuxADC_A or AuxADC_B is controlled by the AuxSPI.
AuxADC_A has two inputs: AuxADC_A1 and AuxADC_A2.
Setting the Select A bit [Register 0x22, Bit 1] determines which
of the multiplexed inputs is connected to AuxADC_A.
The AuxSPI consists of a chip select pin (AUX_SPI_CS, pin
number 4), a clock pin (AUX_SPI_CLK), and a data output pin
(AUX_SPI_SDO multiplex with the SPI_SDO pin). A conversion
is initiated by pulsing the AUX_SPI_CS pin low (AUX_SPI_CS
should remain low during the entire conversion cycle, including
the readback phase). When the conversion is complete, the data
pin, AUX_SPI_SDO, transitions from a logic low to a logic
high. At this point, the user supplies an external clock on the
AUX_SPI_CLK pin. The AUX_SPI_CLK pin should be tied
low when not in use. No data is present on the first rising edge.
The data output bit is updated on the falling edge of the clock
pulse and is settled by and can be latched on the next clock
rising edge. The data arrives serially, MSB first. The AuxSPI
runs at a rate up to 16 MHz.
Operation of the Aux_SPI requires that 3-wire SPI mode be
used, disabling the SDO pin. If the controller is a 4-wire
interface, a method of connecting the 3-wire AD9861 interface
to the 4-wire controller is suggested in Figure 75.
An example of an AuxSPI access is shown in Figure 75. In the
AuxSPI configuration, a start convert is initiated by applying a
rising edge to the Aux_SPI_CS pin. A rising edge on the
Aux_SPI_DO pin indicates that a conversion is done. Supplying
a clock to the Aux_SPI_CLK then outputs data on the
Aux_SPI_DO pin, MSB first.
Figure 75. Diagram to Connect 3-Wire SPI to a 4-Wire SPI Controller
Refsel A/B
[Register 0x22,
Bit 2/Bit 5]
0
1
1
1
CONTROLLER
SPI_CS[x]
SPI_CLK
SPI_DI
Notes
Default mode.
Decouple at AUXADC_REF pin.
VREF voltage from Rx path.
Decouple at AUXADC_REF pin.
Force and decouple at
AUXADC_REF pin.
AD986x
SPI_CS
SPI_CLK
SPI_SDIO
03606-0-006