AD9879 Analog Devices, AD9879 Datasheet - Page 21
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AD9879
Manufacturer Part Number
AD9879
Description
Mixed Signal Front End Set Top Box, Cable Modem (MxFE®)
Manufacturer
Analog Devices
Datasheet
1.AD9879.pdf
(32 pages)
Specifications of AD9879
Resolution (bits)
12bit
# Chan
5
Sample Rate
29MSPS
Interface
Par
Analog Input Type
Diff-Uni
Ain Range
2 V p-p
Adc Architecture
Pipelined
Pkg Type
QFP
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When this bit is set default low, the AD9879 serial port is in
MSB-first format. In MSB-first mode, the instruction byte and
data bytes must be written from the MSB to the LSB. In MSB-
first mode, the serial port internal byte address generator
decrements for each byte of the multibyte communication cycle.
When incrementing from 0x1F, the address generator changes
to 0x00. When decrementing from 0x00, the address generator
changes to 0x1F.
NOTES ON SERIAL PORT OPERATION
The AD9879 serial port configuration bits reside in Bits 6 and 7
of Register 0x00. It is important to note that the configuration
changes immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register may occur
during the middle of the communication cycle. Care must be
taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.
SCLK
SCLK
SDIO
SDIO
SDO
SDO
CS
CS
R/W N1
A0
Figure 10. Serial Register Interface Timing MSB First
Figure 11. Serial Register Interface Timing LSB First
INSTRUCTION CYCLE
A1
INSTRUCTION CYCLE
A2
N0
A3
A4
A4
A3
N0
A2
N1 R/W D0 0 D1 0 D2 0
A1
A0 D7 n D6 n
D0 0 D1 0 D2 0
D7 n D6 n
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
D2 0 D1 0 D0 0
D2 0 D1 0 D0 0
D6 n D7 n
D6 n D7 n
Rev. A | Page 21 of 32
The same considerations apply to setting the reset bit in
Register 0x00. All other registers are set to their default values,
but the software reset does not affect the bits in Register 0x00.
It is recommended to use only single-byte transfers when
changing serial port configurations or initiating a software
reset.
A write to Bits 1, 2, and 3 of Register 0x00 with the same logic
levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows
the user to reprogram a lost serial port configuration and to
reset the registers to their default values.
A second write to Register 0x00 with the reset bit low and the
serial port configuration as specified above (XY) reprograms
the OSCIN multiplier setting. A changed f
stable after a maximum of 200 f
SCLK
SCLK
SDIO
SDIO
SDO
CS
CS
Figure 12. Timing Diagram for Register Write to AD9879
INSTRUCTION BIT 7
t
t
Figure 13. Timing Diagram for Register Read
DS
DS
DATA BIT N
t
PWH
t
DH
t
SCLK
t
PWL
INSTRUCTION BIT 6
MCLK
DATA BIT N – 1
t
DV
cycles (wake-up time).
SYSCLK
frequency is
AD9879