AD7675 Analog Devices, AD7675 Datasheet - Page 13

• Manufacturer Part Number: AD7675
• Manufacturer: Analog Devices

Specifications of AD7675

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: QFP

Care should also be taken with the reference temperature coeffi-
cient of the voltage reference which directly affects the full-scale
accuracy if this parameter matters. For instance, a ± 15 ppm/°C
tempco of the reference changes the full scale by ± 1 LSB/°C.
V
to AVDD – 1.85 V. The benefit here is the increased SNR
obtained as a result of this increase. Since the input range is
defined in terms of V
range to make it a ± 3 V input range with an AVDD above
4.85 V. The theoretical improvement as a result of this increase
in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical
quantization noise, however, the observed improvement is
approximately 1 dB. The AD780 can be selected with a 3 V
reference voltage.
Power Supply
The AD7675 uses three sets of power supply pins: an analog
5 V supply AVDD, a digital 5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD
supply allows direct interface with any logic working between
2.7 V and DVDD + 0.3 V. To reduce the number of supplies
needed, the digital core (DVDD) can be supplied through a
simple RC filter from the analog supply as shown in
Figure 5. The AD7675 is independent of power supply
sequencing once OVDD does not exceed DVDD by more than
0.3 V, and thus free from supply voltage induced latchup.
Additionally, it is very insensitive to power supply variations
over a wide frequency range as shown in Figure 9.
POWER DISSIPATION
The AD7675 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows a significant
power saving when the conversion rate is reduced as shown in
Figure 10. This feature makes the AD7675 ideal for very low
power battery applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
REV. A
REF
, as mentioned in the specification table, could be increased
75
70
65
60
55
50
45
40
35
1k
Figure 9. PSRR vs. Frequency
10k
REF
, this would essentially increase the
FREQUENCY – Hz
100k
1M
10M
–13–
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7675 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The CNVST signal operates independently of
CS and RD signals.
For true sampling applications, the recommended operation of
the CNVST signal is as follows:
CNVST must be held high from the previous falling edge of
BUSY, and during a minimum delay corresponding to the
acquisition time t
conversion is initiated and BUSY signal goes high until the
completion of the conversion. Although CNVST is a digital
signal, it should be designed with this special care with fast,
clean edges and levels, with minimum overshoot and under-
shoot or ringing.
For applications where the SNR is critical, the CNVST signal should
have a very low jitter. Some solutions to achieve that are to use a
dedicated oscillator for CNVST generation or, at least, to clock
it with a high frequency low jitter clock, as shown in Figure 5.
CNVST
MODE
BUSY
100k
Figure 10. Power Dissipation vs. Sample Rate
10k
100
0.1
ACQUIRE
1k
10
1
10
t
t
Figure 11. Basic Conversion Timing
3
5
8
100
; then, when CNVST is brought low, a
t
CONVERT
1
t
7
t
SAMPLING RATE – SPS
4
1k
t
t
6
2
10k
ACQUIRE
t
8
100k
AD7675
1M
CONVERT