AD7898 Analog Devices, AD7898 Datasheet - Page 10

• Manufacturer Part Number: AD7898
• Description: 5V, 12-Bit, Serial 220 kSPS ADC in a 8-Lead Package
• Manufacturer: Analog Devices

Specifications of AD7898

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 220kSPS
• Interface: Ser
• Analog Input Type: SE-Bip
• Ain Range: Bip (Vref),Bip (Vref) x 4,Bip 10V,Bip 2.5V
• Adc Architecture: SAR
• Pkg Type: SOIC

AD7898
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7898.
The GND pin is connected to the analog ground plane of the
system. REF IN is connected to a decoupled 2.5 V supply from
a reference source, the AD780. This provides the analog refer-
ence for the part. The AD7898 is connected to a V
the serial interface is connected to a 3 V microprocessor. The
V
as the microprocessor to allow a 3 V logic interface. The conver-
sion result from the AD7898 is output in a 16-bit word with
four leading zeros followed by the MSB of the 12-bit result. For
applications where power consumption is of concern, the power-
down mode should be used between conversions or bursts of
several conversions to improve power performance. See Modes
of Operation section.
V
The AD7898 has the V
at which the Serial Interface operates. V
easily interface to both 3 V and 5 V processors. For example, if
the AD7898 were operated with a V
pin could be powered from a 3 V supply. The AD7898 has good
dynamic performance with a V
interface to 3 V digital parts. Care should be taken to ensure
V
Maximum Ratings section).
Track/Hold Section
The track/hold amplifier on the analog input of the AD7898
allows the ADC to accurately convert an input sine wave of full-
scale amplitude to 12-bit accuracy. The input bandwidth of the
track/hold is greater than the Nyquist rate of the ADC even
when the ADC is operated at its maximum throughput rate of
220 kSPS (i.e., the track/hold can handle input frequencies in
excess of 112 kHz). The track/hold amplifier acquires an input
signal to 12-bit accuracy in less than 0.5 µs.
The operation of the track/hold is essentially transparent to the
user. When in operating Mode 0, the track/hold amplifier goes
from its tracking mode to its hold mode at the start of conversion
(i.e., the falling edge of CONVST). The aperture time for the
track/hold (i.e., the delay time between the external CONVST
signal and the track/hold actually going into hold) is typically
15 ns. At the end of conversion (after 3.3 µs max), the part
returns to its tracking mode. The acquisition time of the track/
hold amplifier begins at this point.
DRIVE
DRIVE
DRIVE
2.5V OR
INPUT
pin of the AD7898 is connected to the same 3 V supply
Feature
does not exceed V
10V
Figure 5. Typical Connection Diagram
V
V
GND
DD
IN
0.1 F
10 F
AD7898
REF IN
DRIVE
CS/CONVST
DD
0.1 F
AD780
2.5V
by more than 0.3 V (see Absolute
SDATA
feature. V
V
SCLK
DRIVE
DD
5V
SUPPLY
of 5 V while still being able to
DD
DRIVE
of 5 V, and the V
DRIVE
10 F
INTERFACE
SERIAL
controls the voltage
allows the ADC to
0.1 F
DD
SUPPLY
C/ P
3V
of 5 V,
DRIVE
–10–
When in operating in Mode 1, the falling edge of CS will put
track-and-hold into hold mode. On the 14th SCLK falling edge
after the falling edge of CS, the track-and-hold will go back into
track (see Serial Interface section). The acquisition time of the
track/hold amplifier begins at this point.
Reference Input
The reference input to the AD7898 is buffered on-chip with a
maximum reference input current of 1 µA. The part is specified
with a 2.5 V reference input voltage. Errors in the reference
source will result in gain errors in the AD7898’s transfer func-
tion and will add to the specified full-scale errors on the part.
Suitable reference sources for the AD7898 include the AD780
and AD680 precision 2.5 V references.
SERIAL INTERFACE
The serial interface to the AD7898 consists of just three wires: a
serial clock input (SCLK), the serial data output (SDATA) and
a CS/CONVST input depending on the mode of operation.
This allows for an easy-to-use interface to most microcontrol-
lers, DSP processors and shift registers. There is also a V
pin that allows the serial interface to connect directly to either
3 V or 5 V processor systems independent of V
interface operation is different in Mode 0 and Mode 1 operation
and is determined by which mode is selected. Upon power-up,
the default mode of operation is Mode 0. To select Mode 1
operation see the Mode Selection section. The serial interface
operation in Mode 0 and Mode 1 is described in detail in the
Operating Modes section.
OPERATING MODES
Mode 0 Operation
The timing diagram in Figure 6 shows the AD7898 operating in
Mode 0 where the falling edge of CONVST starts conversion
and puts the track/hold amplifier into its hold mode. The con-
version is complete 3.3 µs max after the falling edge of CONVST,
and new data from this conversion is available in the output
register of the AD7898. A read operation accesses this data.
This read operation consists of 16 clock cycles and the length of
this read operation will depend on the serial clock frequency.
For the fastest throughput rate (with a serial clock of 15 MHz,
5 V operation) the read operation will take 1.066 µs. Once the
read operation has taken place, the required quiet time should
be allowed before the next falling edge of CONVST to optimize
the settling of the track/hold amplifier before the next conver-
sion is initiated. A serial clock of less than 15 MHz can be used,
but this will, in turn, mean that the throughput time will increase.
The read operation consists of 16 serial clock pulses to the out-
put shift register of the AD7898. After 16 serial clock pulses, the
shift register is reset, and the SDATA line is three-stated. If
there are more serial clock pulses after the 16th clock, the shift
register will be moved on past its reset state. However, the shift
register will be reset again on the falling edge of the CONVST
signal to ensure that the part returns to a known state after every
conversion cycle. As a result, a read operation from the output
register should not straddle the falling edge of CONVST as
the output shift register will be reset in the middle of the read
operation, and the data read back into the microprocessor will
appear invalid.
DD
. The serial
REV. A
DRIVE