AD7856 Analog Devices, AD7856 Datasheet - Page 4

• Manufacturer Part Number: AD7856
• Description: 5 V Single-Supply, 8-Channel, 14-Bit, 285 kSPS, Serial Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7856

• Resolution (bits): 14bit
• # Chan: 8
• Sample Rate: 285kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

TIMING SPECIFICATIONS
AD7856
Parameter
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
Specifications subject to change without notice.
CLKIN
SCLK
1
2
CONVERT
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CAL
CAL1
CAL2
Sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Table X and timing diagrams for different interface modes and calibration.
Mark/Space ratio for the master clock input is 40/60 to 60/40.
The CONVST pulsewidth here only applies for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply
(see Power-Down section).
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
t
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
relinquish time of the part and is independent of the bus loading.
t
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
12
14
3
4
4
4
5
6
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
2
500
6
6
100
50
3.5
–0.4 t
30
30
45
30
20
0.4 t
0.4 t
30
30/0.4 t
50
90
50
2.5 t
2.5 t
41.7
37.04
4.63
A Version
0.4 t
Limit at T
SCLK
SCLK
CLKIN
CLKIN
SCLK
SCLK
SCLK
MIN
, T
K Version
500
4
4
100
50
5.25
–0.4 t
50
50
75
40
20
0.4 t
0.4 t
30
30/0.4 t
50
90
50
2.5 t
2.5 t
62.5
55.5
6.94
MAX
0.4 t
1
SCLK
SCLK
CLKIN
CLKIN
(V
SCLK
SCLK
DD
SCLK
= 5 V; T
Units
kHz min
MHz max
MHz max
ns min
ns max
ns min
ns min/max
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ms typ
ms typ
ms typ
s max
A
= T
MIN
to T
MAX
, unless otherwise noted. A Grade: f
–4–
Internal DAC Plus System Full-Scale Cal Time, Master
Description
Master Clock Frequency
CONVST Pulsewidth
CONVST to BUSY Propagation Delay
Conversion Time = 20 t
SYNC to SCLK Setup Time (Noncontinuous SCLK Input)
SYNC to SCLK Setup Time (Continuous SCLK Input)
Delay from SYNC Until DOUT 3-State Disabled
Delay from SYNC Until DIN 3-State Disabled
Data Access Time After SCLK
Data Setup Time Prior to SCLK
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK to SYNC Hold Time (Noncontinuous SCLK)
(Continuous SCLK)
Delay from SYNC Until DOUT 3-State Enabled
Delay from SCLK to DIN Being Configured as Output
Delay from SCLK to DIN Being Configured as Input
CAL to BUSY Delay
CONVST to BUSY Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(250026 t
Clock Dependent (222228 t
System Offset Calibration Time, Master Clock Dependent
(27798 t
CLKIN
CLKIN
)
)
12
, quoted in the timing characteristics is the true bus
CLKIN
DD
14
) and timed from a voltage level of 1.6 V.
, quoted in the Timing Characteristics is the
CLKIN
CLKIN
)
= 6 MHz; K Grade: f
CLKIN
= 4 MHz.)
REV. A