AD7721 Analog Devices, AD7721 Datasheet - Page 12

• Manufacturer Part Number: AD7721
• Description: CMOS, 12-/16-Bit, 312.5 kHz/468.75 kHz Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7721

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: n/a
• Interface: Par,Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7721
PARALLEL INTERFACE
Read Operation
The device defaults to parallel mode if CS, RD and WR are not
tied to DGND together. Figure 11 shows a timing diagram for
reading from the AD7721 in the parallel mode. When operating
the device in parallel mode, CS and RD should be tied to
DGND permanently except when control information is being
written to the AD7721. DRDY goes high for 2 clock cycles to
indicate that new data is available from the interface. The
AD7721 outputs this data after the falling edge of DRDY. This
DRDY pin can be used to drive an edge-triggered interrupt of a
microprocessor.
RFS (I) / DRDY (O)
NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.
DATA OUT (O)
SCLK (O)
DB0–DB11 (O)
DB0–DB11 (I)
NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.
NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.
DRDY (O)
WR (I)
CS (I)
CS (I)
RD (I)
t
1
t
3
t
2
DB15
Figure 11. Parallel Mode Output Register Read
Figure 10. Serial Mode Output Register Read
DB14
Figure 12. Write Timing Diagram
DB13
t
10
t
4
t
DB12
t
11
5
–12–
DB11
t
12
Write Operation
The write operation is used to write data into the control regis-
ter. The outputs of the control register select the analog input
range, allow the part to be put into power-down (standby)
mode, define the function of the DVAL/SYNC pin, and initiate
the calibration routine. After power-up and after at least 16
clock cycles, the control register must be written to. A cali-
bration must also be performed at least once after power-up to
set the calibration registers. The function of each bit in the
control register is shown in Table I. When writing to the con-
trol register, the RD pin must be taken high so that the pins D0
to D11 are configured as inputs.
t
9
DB10
t
6
VALID DATA
t
13
t
14
DB0
t
15
t
7
REV. A
t
8