AD7721 Analog Devices, AD7721 Datasheet - Page 4

• Manufacturer Part Number: AD7721
• Description: CMOS, 12-/16-Bit, 312.5 kHz/468.75 kHz Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7721

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: n/a
• Interface: Par,Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7721
TIMING CHARACTERISTICS
Parameter
Serial Interface
f
t
t
t
t
t
t
t
t
t
t
t
Parallel Interface
f
t
t
Read Operation
t
t
t
Write Operation
t
t
t
NOTES
The timing is measured with a load of 50 pF on SCLK and DRDY. SCLK can be operated with a load capacitance of 50 pF maximum.
1
2
3
4
5
Sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
All digital outputs are timed with the load circuit below and, except for t
The AD7721 is production tested with f
t
t
CLK
CLK LO
CLK HI
1
2
3
4
5
6
7
8
9
CLK
CLK LO
CLK HI
10
11
12
13
14
15
ization to operate with CLK frequencies down to 100 kHz.
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus
relinquish time of the part and, as such, is independent of external bus loading capacitance.
2
8
4
5
is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V.
and t
3
3
15
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then
Limit at T
(A, S Versions)
100
15
0.45
0.45
t
t
20
t
t
25
0
0
20
32
100
10
0.45
0.45
2
30
32
35
20
0
CLK
CLK HI
CLK HI
CLK LO
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CLK
t
CLK
t
t
CLK
CLK
at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by character-
– 10
t
t
t
t
CLK
CLK
CLK
CLK
1, 2
MIN
, T
(AV
unless otherwise noted)
MAX
DD
OUTPUT
= +5 V
PIN
TO
50pF
Units
kHz min
MHz max
ns min
ns min
ns nom
ns min
ns max
ns nom
ns nom
ns max
ns min
ns min
ns max
ns nom
kHz min
MHz max
ns min
ns min
ns nom
ns max
ns nom
ns min
ns min
ns min
2
C
, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last.
L
5%; DV
200 A
1.6mA
–4–
DD
= +5 V
I
I
OH
OL
Conditions/Comments
Master Clock Frequency
15 MHz for Specified Performance
Master Clock Input Low Time
Master Clock Input High Time
DRDY High Time
RFS Low to SCLK Falling Edge Setup Time
RFS Low to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Rising Edge to Data Valid Delay
RFS to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of RFS
Period between Consecutive DRDY Rising Edges
Master Clock Frequency
10 MHz for Specified Performance
Master Clock Input Low Time
Master Clock Input High Time
DRDY High Time
Data Access Time after Falling Edge of DRDY
Period between Consecutive DRDY Rising Edges
WR Pulse Width
Data Valid to WR High Setup Time
Data Valid to WR High Hold Time
5%; AGND = DGND = 0 V, REFIN = +2.5 V
+1.6V
REV. A