AD7891 Analog Devices, AD7891 Datasheet - Page 4

• Manufacturer Part Number: AD7891
• Description: True Bipolar Input, Single Supply, Parallel, 8-Channel, 12-Bit High Speed Data Acquisition System
• Manufacturer: Analog Devices

Specifications of AD7891

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 500kSPS
• Interface: Par,Ser
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 10V,Bip 2.5V,Bip 5.0V,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: LCC,QFP

AD7891
TIMING CHARACTERISTICS
Parameter
t
Parallel Interface
Serial Interface
NOTES
1
2
3
4
Specifications subject to change without notice.
CONV
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of 5 V) and timed from a voltage level of 1.6 V.
See Figures 2, 3, and 4.
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
11
13
14
17
18A
19
20
21
22
10
12
15
16
18
3
4
3
3
3
4
4
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
A, B, Y Versions
1.6
0
35
25
5
0
35
55
35
25
5
30
30
20
25
25
5
15
20
0
30
0
30
20
15
10
30
1, 2
OUTPUT
PIN
TO
50pF
Unit
ms max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
–4–
200 A
1.6mA
1.6V
Test Conditions/Comments
Conversion Time
CS to RD/WR Setup Time
Write Pulse Width
Data Valid to Write Setup Time
Data Valid to Write Hold Time
CS to RD/WR Hold Time
CONVST Pulse Width
EOC Pulse Width
Read Pulse Width
Data Access Time after Falling Edge of RD
Bus Relinquish Time after Rising Edge of RD
RFS Low to SCLK Falling Edge Setup Time
RFS Low to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Rising Edge to Data Valid Hold Time
SCLK Rising Edge to Data Valid Delay
RFS to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of RFS
Bus Relinquish Time after Rising Edge of SCLK
TFS Low to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS Low to SCLK Falling Edge Hold Time
REV. D