AD7716 Analog Devices, AD7716 Datasheet
AD7716
Specifications of AD7716
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AD7716 Summary of contents
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... High Accuracy Instrumentation Seismic Systems GENERAL DESCRIPTION The AD7716 is a signal processing block for data acquisition systems capable of processing four channels with band- widths 584 Hz. Resolution is 22 bits and the usable dynamic range varies from 111 dB with an input bandwidth of 36 ...
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... AD7716–SPECIFICATIONS 5 –5 V 5%; AGND = DGND = Resistance = 750 with AGND at each A Parameter B Version STATIC PERFORMANCE Resolution 22 Integral Linearity Error 0.003 0.006 Gain Error 1 Gain Match Between Channels 0.5 Gain TC 30 Offset Error 0.2 Offset Match Between Channels 0.1 Offset TC 4 Noise ...
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... OUTPUT +2.1V PIN C L 50pF I 200 DB1 DB2 DB3 DB4 DB5 (DB9) (DB10) (DB11) (DB12) (DB13) Figure 2. Control Register Timing Diagram –3– AD7716 Filter Settling Time to Absolute Group 0.0007% FS (ms) Delay (ms) 1.35 0.675 2.7 1.35 5.4 2.7 10.8 5.4 21 –5 V 5%; AGND = DD SS Conditions/Comments ...
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... Sample tested at + ensure compliance. All input signals are specified with (10 and timed from a voltage level of 1 See Figures 1 and 3. 3 CLKIN duty cycle range is 40% to 60%. 4 The AD7716 is production tested with MHz in the slave mode guaranteed by characterization to operate at 400 kHz and 8 MHz in master mode. CLKIN 5 Specified using 10% and 90% points on waveform of interest measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0 ...
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... Sample tested at + ensure compliance. All input signals are specified with (10 and timed from a voltage level of 1 See Figures 1 and 4. 3 CLKIN duty cycle range is 40% to 60%. 4 The AD7716 is production tested with MHz in the slave mode guaranteed by characterization to operate at 400 kHz. CLKIN 5 Specified using 10% and 90% points on waveform of interest measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0 ...
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... rms –6– WARNING! ESD SENSITIVE DEVICE PLCC PINOUT MODE AD7716 IN TOP VIEW 34 NC (Not to Scale) 33 CASCIN 32 CASCOUT 31 V REF AGND ...
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... V Reference Input, Nominally 2.5 V. REF AGND Analog Ground. Ground reference for analog circuitry. DGND Digital Ground. Ground return for digital circuitry. A 1–A 4 Analog Input Pins. The analog input range is 2 REV. A PIN DESCRIPTION –7– AD7716 & ...
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... LSB) width. Differential Linearity Error is expressed in LSBs. A differential linearity specification of 1 LSB or less guarantees no missed codes to the full resolution of the device. The AD7716 has no missed codes guaranteed to 21 bits with a cutoff frequency of 146 Hz. GAIN ERROR Gain Error is the deviation of the last code transition (111 ...
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... After power- there is a step change in the input voltage, there is a settling time before valid data is obtained. DIGITAL FILTERING The AD7716’s digital filter behaves like an analog filter, with a few minor differences. First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion pro- cess ...
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... This means that there are frequency bands, f 3dB to FC2) where noise passes unattenuated to the output. How- ever, due to the AD7716’s high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broad- band noise is filtered. In spectral analysis applications important to note that at- tenuation at half the output update rate ...
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... Any extra external impedances result in a longer over- all charge time resulting in extra gain errors on the analog input. The AD7716 has a quite large gain error (1% FSR) due to the fact that there is no on-chip calibration. Thus, even an extra 10 k source resistance and 50 pF source capacitance will have no significant effect on this ...
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... Control register bit, DB15 (A3), acts as an extra address bit which must always be set enable programming of the AD7716 set to 0, then the programmed word is ignored. This allows the user to bypass the AD7716 control register and use the serial stream from the DSP or microcomputer to pro- gram other serial peripheral devices ...
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... DRDY output indicates that the output shift register has been updated. There are two interface modes. One is the master mode, where the AD7716 is the master in the sys- tem and the processor to which it is communicating is the slave. The other mode is the slave mode, where the AD7716 is the slave and the processor is the system master ...
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... The SPORT0 RFSDIV Register (0 the minimum value of “000F.” Finally the IRQ2 interrupt should be enabled. The DSP will now wait for an interrupt from the AD7716. This interrupt is generated by the AD7716 DRDY line going low. If the interrupt service routine is set for autobuffered mode with a ...
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... The optimum setup for reading all four channels of the AD7716 into the DSP56001 is six 24-bit reads. This will provide 144 clock edges to shift out the 128 bits of data in the AD7716 output shift register. The first clock applied to the AD7716 will clock out DB21 ...
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... AD7716 Multibandwidth System Some applications may require multiple AD7716’s with differ- ent bandwidths programmed to each device. The best way to accomplish this is shown in Figure 12. The master mode inter- face is used for this example but the slave mode may also be used. The example shows an 8-channel system with Device #0 in the system programmed for a 292 Hz cutoff frequency and Device #1 programmed for a 146 Hz cutoff frequency ...