AD7716 Analog Devices, AD7716 Datasheet - Page 3

• Manufacturer Part Number: AD7716
• Description: CMOS, 4-Channel, 22-Bit Data Acquisition System
• Manufacturer: Analog Devices

Specifications of AD7716

• Resolution (bits): 22bit
• # Chan: 4
• Sample Rate: 570kSPS
• Interface: Ser
• Analog Input Type: SE-Bip
• Ain Range: Bip 2.5V
• Adc Architecture: Sigma-Delta
• Pkg Type: LCC,QFP

N
0
1
2
3
4
NOTE
Usable Dynamic Range is defined as the ratio of the rms full-scale reading (sine wave input) to the rms noise of the converter.
CONTROL REGISTER TIMING CHARACTERISTICS
DGND = 0 V; f
Parameter
t
t
t
t
t
t
NOTES
1
2
3
REV. A
Sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
See Figure 2.
CLKIN Duty Cycle range is 40% to 60%.
1
2
3
4
5
6
Programmed Cutoff
Frequency (Hz)
584
292
146
73
36.5
Table I. Typical Usable Dynamic Range, RMS Noise and Filter Settling Time vs. Filter Cutoff Frequency
CLKIN
= 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DV
SDATA (I)
SCLK (I)
TFS (I)
Output Update
Rate (Hz)
2232
1116
558
279
140
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
Limit at T
(B Version)
1/f
77
30
20
10
20
t
t
3
(DB8)
4
DB0
CLKIN
t
1
t
t
5
2
t
2
MIN
(DB9)
DB1
Figure 2. Control Register Timing Diagram
, T
OUTPUT
MAX
PIN
TO
Usable Dynamic
Range (dB)
99
102
105
108
111
(DB10)
DB2
50pF
C
L
200 A
1.6mA
(DB11)
DB3
DD
–3–
; unless otherwise noted)
I
I
OH
OL
(DB12)
RMS Noise
( V)
21
14
10
7
5
1, 2
DB4
Units
ns min
ns min
ns min
ns min
ns min
ns min
(AV
+2.1V
DD
(DB13)
DB5
= DV
DD
Filter Settling Time to
1.35
2.7
5.4
10.8
21.6
0.0007% FS (ms)
= +5 V
(DB14)
DB6
(DB15)
5%; AV
DB7
t
6
Conditions/Comments
SCLK Period
SCLK Width
TFS Setup Time
SDATA Setup Time
SDATA Hold Time
TFS Hold Time
SS
= –5 V
Absolute Group
0.675
1.35
2.7
5.4
10.8
Delay (ms)
AD7716
5%; AGND =