CS8406-CZZ Cirrus Logic Inc, CS8406-CZZ Datasheet - Page 20

• Manufacturer Part Number: CS8406-CZZ
• Description: IC XMITTER DGTL 192KHZ 28TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Transmitterr

Specifications of CS8406-CZZ

• Package / Case: 28-TSSOP
• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Operating Supply Voltage: 3.3 V / 5.0 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1017 - BOARD EVAL FOR CS8416 RCVR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1121-5

20
8.4
8.5
7
0
7
0
MMTCS - Select A or B channel status data to transmit in Mono Mode
Default = ‘0’
0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe
1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS
data. If MMTLR = 1, use the right channel CS data.
MMTLR - Channel Selection for AES Transmitter Mono Mode
Default = ‘0’
0 - Use left channel input data for consecutive subframe outputs
1- Use right channel input data for consecutive subframe outputs
Data Flow Control (03h)
The Data Flow Control register configures the flow of audio data. The output data should be muted prior to
changing bits in this register to avoid transients.
TXOFF - AES3 Transmitter Output Driver Control
Default = ‘0
0 - AES3 transmitter output pin drivers normal operation
1 - AES3 transmitter output pin drivers drive to 0 V.
AESBP - AES3 bypass mode selection
Default = ‘0’
0 - Normal operation
1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL
threshold digital input.
Clock Source Control (04h)
This register configures the clock sources of various blocks. In conjunction with the Data Flow Control reg-
ister, various Receiver/Transmitter/Transceiver modes may be selected.
RUN - Controls the internal clocks, allowing the CS8406 to be placed in a “powered down” low current con-
sumption, state.
Default = ‘0’
0 - Internal clocks are stopped. Internal state machines are reset. The fully static
1 - Normal part operation. This bit must be set to 1 to allow the CS8406 to begin operation.
CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector. If these bits
are changed during normal operation, always stop the CS8406 first (RUN = 0), write the new value, then
start the CS8406 (RUN = 1).
control port registers are operational, allowing registers to be read or changed. Reading and
writing the U and C data buffers is not possible. Power consumption is low.
All input clocks should be stable in frequency and phase when RUN is set to 1.
TXOFF
RUN
6
6
AESBP
CLK1
5
5
CLK0
4
0
4
3
0
3
0
2
0
2
0
1
0
1
0
CS8406
DS580F5
0
0
0
0