AD5755-1 Analog Devices, AD5755-1 Datasheet
AD5755-1
Specifications of AD5755-1
Available stocks
Related parts for AD5755-1
AD5755-1 Summary of contents
Page 1
... APPLICATIONS Process control Actuator control PLCs HART network connectivity GENERAL DESCRIPTION The AD5755 quad, voltage and current output DAC that operates with a power supply range from −26 +33 V. On-chip dynamic power control minimizes package power AV SS –15V/0V AGND DV ...
Page 2
... Typical Performance Characteristics ........................................... 16 Voltage Outputs .......................................................................... 16 Current Outputs ......................................................................... 20 DC-to-DC Block ......................................................................... 24 Reference ..................................................................................... 25 General ......................................................................................... 26 Terminology .................................................................................... 27 Theory of Operation ...................................................................... 29 DAC Architecture ....................................................................... 29 Power-On State of the AD5755-1 ............................................. 29 Serial Interface ............................................................................ 30 Transfer Function ....................................................................... 30 Registers ........................................................................................... 31 Programming Sequence to Write/Enable the Output Correctly ...................................................................................... 32 Changing and Reprogramming the Range ............................. 32 Data Registers ............................................................................. 33 Control Registers ........................................................................ 35 Readback Operation .................................................................. 38 Device Features ...
Page 3
... Changes to Figure 12 ...................................................................... 16 Changes to Figure 21 ...................................................................... 18 Changes to Figure 37 ...................................................................... 20 Changes to Figure 44 ...................................................................... 22 Changes to Figure 71 ...................................................................... 29 Changes to Power-On State of the AD5755-1 Section ............... 30 Changes to Table 17 ........................................................................ 35 Changes to Readback Operation section and Table 26 .............. 38 Changes to Voltage Output Short-Circuit Protection Section .. 40 Changes to Figure 78 ...................................................................... 41 Changes to Figure 82 ...................................................................... 44 Changes to Figure 83, Figure 84, and Figure 85 ...
Page 4
... SYNC SDO GAIN REG A FAULT OFFSET REG A STATUS REGISTER WATCHDOG ALERT TIMER (SPI ACTIVITY) REFOUT VREF REFERENCE DAC CHANNEL A REFIN BUFFERS DAC CHANNEL B AD1 DAC CHANNEL C AD5755-1 DAC CHANNEL D AD0 SW POWER 7.4V TO 29.5V CONTROL R2 16 DAC + DAC A REG A R1 VOUT RANGE SCALING ...
Page 5
... FSR 16/8 mA kΩ µF 0.06 Ω 50 µV/V 24 µV Rev Page AD5755-1 = 300 Ω; all specifications MIN MAX Test Conditions/Comments AV = −15 V, loaded and unloaded 25°C A Drift after 1000 hours 150° ±5 V, ±10 V ranges ...
Page 6
... AD5755-1 Parameter 1 Min CURRENT OUTPUT Output Current Ranges Resolution 16 ACCURACY (EXTERNAL R ) SET Total Unadjusted Error (TUE) −0.05 TUE Long-Term Stability Relative Accuracy (INL) −0.006 Differential Nonlinearity (DNL) −1 Offset Error −0.05 Offset Error Drift 2 Gain Error −0.05 Gain TC 2 Full-Scale Error − ...
Page 7
... JEDEC compliant V 0 µA Per pin 2.6 pF Per pin 0.4 V Sinking 200 µA V Sourcing 200 µA +1 µA 2 kΩ pull-up resistor kΩ pull-up resistor −10.8/0 V 5.5 V 5.5 V Rev Page AD5755-1 = 25° 150°C J Figure 64 Figure 65 Figure ...
Page 8
... AD5755-1 Parameter 1 Min −11 SS −1 BOOST I 6 BOOST Power Dissipation 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization; not production tested. 3 For voltage output ranges in unipolar supply mode, the INL and TUE are measured beginning from Code 4096. ...
Page 9
... SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated) µs min SYNC high to next SYNC low (digital slew rate control disabled) (single DAC updated) ) and timed from a voltage level of 1 Rev Page AD5755-1 = 300 Ω; all specifications MIN MAX , unless ...
Page 10
... AD5755-1 Timing Diagrams SCLK SYNC t 7 SDIN MSB LDAC V OUT_x LDAC = 0 V OUT_x CLEAR V OUT_x RESET SCLK 1 SYNC MSB SDIN INPUT WORD SPECIFIES REGISTER TO BE READ SDO LSB Figure 3 ...
Page 11
... X X D15 D14 SDO_ STATUS STATUS ENAB Figure 5. Status Readback During Write 200µ OUTPUT OH PIN 50pF 200µ Figure 6. Load Circuit for SDO Timing Diagram Rev Page AD5755-1 MSB STATUS STATUS (MIN) OR (MAX) ...
Page 12
... AD5755-1 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents 100 mA do not cause SCR latch-up. Table 4. Parameter Rating AGND, DGND −0 + BOOST_x AV to AGND, DGND +0 − −0 + AGND − ...
Page 13
... AD1 6 SYNC 7 AD5755-1 SCLK 8 TOP VIEW SDIN 9 (Not to Scale) SDO LDAC PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY SS Figure 7. Pin Configuration Rev Page AD5755-1 48 COMP DCDC_C 47 I OUT_C 46 V BOOST_C GNDSW C 42 GNDSW ...
Page 14
... AD5755-1 Pin No. Mnemonic Description 15 ALERT Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a predetermined time. See the Device Features section for more information. 16 Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in ...
Page 15
... Supply Requirements—Slewing sections in the Device Features section for more CC Output Buffer. Connecting a 220 pF capacitor between OUT_D pin allows the voltage output to drive µF. Note that the addition of this capacitor OUT_D Rev Page AD5755-1 stage, which is OUT_x . OUT_C stage, which is OUT_x ...
Page 16
... AD5755-1 TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUTS 0.0015 ±10V RANGE AV ±5V RANGE AV +10V RANGE T +5V RANGE 0.0010 +10V RANGE WITH DCDC 0.0005 0 –0.0005 –0.0010 0 10k 20k 30k 40k CODE Figure 8. Integral Nonlinearity Error vs. DAC Code 1.0 ±10V RANGE AV DD 0.8 ±5V RANGE ...
Page 17
... Rev Page AD5755-1 0 ±5V RANGE ±10V RANGE AV = +15V –15V SS OUTPUT UNLOADED –40 – TEMPERATURE (°C) Figure 17 ...
Page 18
... AD5755-1 0.0020 0.0015 0.0010 0.0005 0V TO 10V RANGE MAX INL 0V TO 10V RANGE MIN INL 25° –26.4V FOR AV > +26. –0.0005 –0.0010 –0.0015 –0.0020 SUPPLY (V) Figure 20. Integral Nonlinearity Error vs +15V –15V 0.8 SS ALL RANGES ...
Page 19
... POC = +15V –15V SS ±10V RANGE T = 25°C A INT_ENABLE = TIME (µs) Figure 30. V vs. Time on Output Enable OUT_x +15V +15V BOOST AV = –15V 25° 100 1k 10k 100k FREQUENCY (Hz) Figure 31. V PSRR vs. Frequency OUT_x AD5755-1 125 10M ...
Page 20
... AD5755-1 CURRENT OUTPUTS 0.0025 AV = +15V –15V 25°C A 0.0015 0.0005 –0.0005 –0.0015 4mA TO 20mA, EXTERNAL R SET 4mA TO 20mA, EXTERNAL R , WITH DC-TO-DC CONVERTER SET 4mA TO 20mA, INTERNAL R SET 4mA TO 20mA, INTERNAL R , WITH DC-TO-DC CONVERTER SET –0.0025 0 10000 20000 30000 40000 CODE Figure 32 ...
Page 21
... SET 0 4mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL T = 25° –26.4V FOR AV > +26. SUPPLY (V) Figure 43. Integral Nonlinearity Error vs. AV /|AV DD Over Supply, Internal R SET AD5755-1 SET SET SET SET SET SET 80 100 ...
Page 22
... AD5755-1 1.0 ALL RANGES 0.8 INTERNAL AND EXTERNAL R SET T = 25° –26.4V FOR AV > +26. 0.4 0.2 DNL ERROR MAX 0 DNL ERROR MIN –0.2 –0.4 –0.6 –0.8 –1 SUPPLY (V) Figure 44. Differential Nonlinearity Error vs. AV 0.012 0.010 0.008 0.006 0.004 4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE 0 ...
Page 23
... LOAD 410kHz SW INDUCTOR = 10µH (XAL4040-103 25° CURRENT (mA +15V +15V BOOST – –15V 25°C A –40 –60 –80 –100 –120 10 100 1k 10k 100k FREQUENCY (Hz) Figure 54. I PSRR vs. Frequency OUT_x AD5755 10M ...
Page 24
... AD5755-1 DC-TO-DC BLOCK 4. 5. 0mA TO 24mA RANGE 1kΩ LOAD 60 EXTERNAL 410kHz SW 55 INDUCTOR = 10µH (XAL4040-103 25° CURRENT (mA) Figure 55. Efficiency at V vs. Output Current (See Figure 80) BOOST_x 90 20mA 0mA TO 24mA RANGE 1kΩ LOAD ...
Page 25
... Figure 63. REFOUT vs. Temperature (When the AD5755-1 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. ...
Page 26
... AD5755-1 GENERAL 450 400 350 300 250 200 150 100 SDIN VOLTAGE (V) Figure 66. DI vs. Logic Input Voltage 25° OUT 0 OUTPUT UNLOADED –2 –4 –6 –8 –10 – VOLTAGE (V) Figure 67. AI /AI vs ...
Page 27
... V/µs. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5755-1 is powered-on specified as the area of the glitch in nV-sec. See Figure 29 and Figure 47. Digital-to-Analog Glitch Impulse ...
Page 28
... AD5755-1 Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000) ...
Page 29
... On-chip dynamic power control minimizes package power dissipation in current mode. DAC ARCHITECTURE The DAC core architecture of the AD5755-1 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 71. The four MSBs of the 16-bit data-word are decoded to drive 15 switches E15. Each of these switches connects one of 15 matched resistors to either ground or the reference buffer output ...
Page 30
... Figure 74. Simplified Serial Interface of Input Loading Circuitry for One DAC Channel TRANSFER FUNCTION Table 6 shows the input code to ideal output voltage relationship for the AD5755-1 for straight binary data coding of the ±10 V output range. Table 6. Ideal Output Voltage to Input Code Relationship Digital Input ...
Page 31
... Description Data DAC Data Register (×4) Used to write a DAC code to each DAC channel. AD5755-1 data bits = D15 to D0. There are four DAC data registers, one per DAC channel. Gain Register (×4) Used to program gain trim per channel basis. AD5755-1 data bits = D15 to D0. There are four gain registers, one per DAC channel. Offset Register (× ...
Page 32
... AD5755-1 PROGRAMMING SEQUENCE TO WRITE/ENABLE THE OUTPUT CORRECTLY To correctly write to and set up the part from a power-on condition, use the following sequence: 1. Perform a hardware or software reset after initial power-on. 2. The dc-to-dc converter supply block must be configured. Set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at ...
Page 33
... DUT_AD0 Table 9. Input Register Decode Bit Description R/W Indicates a read from or a write to the addressed register. DUT_AD1, DUT_AD0 Used in association with the external pins, AD1 and AD0, to determine which AD5755-1 device is being addressed by the system controller. DUT_AD1 DREG2, DREG1, DREG0 Selects whether a data register or a control register is written to ...
Page 34
... AD5755-1 Gain Register The 16-bit gain register, as shown in Table 11, allows the user to adjust the gain of each channel in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 010 possible to write the same gain code to all four DAC channels at the same time by setting the DREG[2:0] bits to 011 ...
Page 35
... Software register D10 EWD WD1 WD0 X 1 ShtCctLim Timeout Period (ms 100 200 pin in the event of a short-circuit condition. OUT_x Rev Page AD5755-1 LSB D15 D14 D13 D12 to D0 CREG2 CREG1 CREG0 Data OUTEN_ALL DCDC_ALL X 1 LSB ...
Page 36
... AD5755-1 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 20 and Table 21. Table 20. Programming DAC Control Register D15 D14 D13 D12 D11 D10 don’t care. ...
Page 37
... D11, in the status register also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication has not been lost between the MCU and the AD5755-1 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC ). Table 22. Programming the Software Register ...
Page 38
... To read back the gain register of Device 1, Channel A on the AD5755-1, implement the following sequence: 1. Write 0xA80000 to the AD5755-1 input register. This configures the AD5755-1 Device Address 1 for read mode with the gain register of Channel A selected. All the data bits, D15 to D0, are don’t cares. 2. ...
Page 39
... Ramp Active This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel). Over TEMP This bit is set if the AD5755-1 core temperature exceeds approximately 150°C. V Fault This bit is set if a fault is detected on the V ...
Page 40
... M is the code in the gain register (default code = the code in the offset register (default code = 2 STATUS READBACK DURING A WRITE The AD5755-1 has the ability to read back the status register contents during every write sequence. This feature is enabled via the STATREAD bit in the main control register. This allows ...
Page 41
... Table 18 and Table 19). OUTPUT ALERT The AD5755-1 is equipped with an ALERT pin. This is an active high CMOS output. The AD5755-1 also has an internal watchdog timer. When enabled, it monitors SPI communica- tions. If 0x195 is not received by the software register within the timeout period, the ALERT pin goes active ...
Page 42
... HART. DIGITAL SLEW RATE CONTROL The slew rate control feature of the AD5755-1 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load ...
Page 43
... DC-to-DC Converter Operation The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step 4 5 drive the AD5755-1 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous ...
Page 44
... The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR component. For the AD5755-1, a low ESR tantalum or ceramic capacitor of 10 µF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature ...
Page 45
... Figure 83 and 8 Figure 84 (V voltage). 4 0.8 0 2.0 2.5 0.7 0.6 0.5 0.4 0.3 0.2 0 Figure 85. AI Rev Page AD5755 0mA TO 24mA RANGE I OUT 500Ω LOAD V BOOST f = 410kHz SW INDUCTOR = 10µH (XAL4040-103 25°C A 0.5 1.0 1.5 2.0 TIME (ms) Current vs. Time for 24 mA Step Through 500 Ω Load CC with External 51 kΩ ...
Page 46
... APPLICATIONS INFORMATION VOLTAGE AND CURRENT OUTPUT RANGES ON THE SAME TERMINAL When using a channel of the AD5755-1, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. There is no conflict with tying the two output pins together because only the voltage output or the current output can be enabled at any one time ...
Page 47
... R D2 LOAD the board. If the AD5755 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. ...
Page 48
... Analog Devices iCoupler® products can provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5755- 1 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 88 shows a 4- channel isolated interface to the AD5755-1 using an ADuM1400. For more information, visit www.analog.com. , close to AV and ...
Page 49
... Rev Page 0.60 MAX PIN 1 INDICATOR 64 1 7.25 EXPOSED PAD 7.10 SQ (BOTTOM VIEW) 6. 0.25 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Description Package Option 64-lead LFCSP_VQ CP-64-3 64-lead LFCSP_VQ CP-64-3 Evaluation Board AD5755-1 ...
Page 50
... AD5755-1 NOTES Rev Page Data Sheet ...
Page 51
... Data Sheet NOTES Rev Page AD5755-1 ...
Page 52
... AD5755-1 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09226-0-11/11(B) Rev Page Data Sheet ...