AD9739A Analog Devices, AD9739A Datasheet - Page 55

• Manufacturer Part Number: AD9739A
• Description: 14-Bit, 2.5 GSPS, RF D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9739A

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): n/a
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
ANALOG INTERFACE CONSIDERATIONS
ANALOG MODES OF OPERATION
The
shown in Figure 169. The quad-switch architecture masks the
code-dependent glitches that occur in a conventional two-switch
DAC. Figure 170 compares the waveforms for a conventional
DAC and the quad-switch DAC. In the two-switch architecture,
a code-dependent glitch occurs each time the DAC switches to
a different state (that is, D1 to D2). This code-dependent glitching
causes an increased amount of distortion in the DAC. In quad-
switch architecture (no matter what the codes are), there are
always two switches transitioning at each half clock cycle, thus
eliminating the code-dependent glitches. However, a constant
glitch occurs at 2 × DACCLK_x because half the internal switches
change state on the rising DACCLK_x edge whereas the other
half change state on the falling DACCLK_x edge.
Another attribute of the quad-switch architecture is that it also
enables the DAC core to operate in one of the following two
modes: normal mode and mix-mode. The mode is selected via
SPI Register 0x08, Bits[1:0], with normal mode being the default
value. In the mix-mode, the output is effectively chopped at the
DAC sample rate. This has the effect of reducing the power of
the fundamental signal while increasing the power of the images
centered around the DAC sample rate, thus improving the
output power of these images.
AD9737A/AD9739A
(NORMAL MODE)
DACCLK_x
DBx[13:0]
Figure 170. Two-Switch and Quad-Switch DAC Waveforms
FOUR-SWITCH
TWO-SWITCH
DAC OUTPUT
DAC OUTPUT
DACCLK_x
Figure 169.
INPUT
DATA
LATCHES
CLK
D
D
D
1
1
1
AD9739A
D
D
D
2
V
V
V
V
2
2
G
G
G
G
1
2
3
4
D
use the quad-switch architecture
D
D
3
3
3
D
V
D
D
4
G
Quad-Switch Architecture
4
4
1
IOUTP
D
D
D
5
5
5
D
D
D
6
6
6
V
D
G
D
D
7
VDD
2
7
7
V
D
D
D
G
8
3
8
8
D
D
D
9
IOUTN
9
9
D
D
D
10
10
10
V
G
t
t
4
Rev. | Page 55 of 64
C
Figure 171 shows the DAC waveforms for mix-mode. This ability
to change modes provides the user the flexibility to place a
carrier anywhere in the first two Nyquist zones, depending
on the operating mode selected. Switching between the analog
modes reshapes the sinc roll-off that is inherent at the DAC output.
The maximum amplitude in both Nyquist zones is impacted by
this sinc roll-off, depending on where the carrier is placed (see
Figure 172). As a practical matter, the usable bandwidth in the
third Nyquist zone becomes limited at higher DAC clock rates
(that is, >2 GSPS) when the output bandwidth of the DAC core
and the interface network (that is, balun) contributes to
additional roll-off.
FOUR-SWITCH
(
f
DAC OUTPUT
S
–10
–15
–20
–25
–30
–35
–5
DACCLK_x
MIX MODE)
0
0FS
Figure 172. Sinc Roll-Off for Each Analog Operating Mode
INPUT
DATA
NYQUIST ZONE
0.25FS
FIRST
D
Figure 171. Mix-Mode DAC Waveforms
D
1
1
–D
1
D
D
2
0.50FS
–D
2
2
D
D
FREQUENCY (Hz)
3
–D
NYQUIST ZONE
3
3
MIX MODE
D
SECOND
D
4
0.75FS
–D
4
4
D
D
5
–D
5
5
AD9737A/AD9739A
D
D
NORMAL
6
1.00FS
–D
MODE
6
6
D
D
7
–D
7
NYQUIST ZONE
7
D
8
D
–D
1.25FS
THIRD
8
8
D
9
D
–D
9
9
D
10
D
–D
10
1.50FS
10
t