AD9739A Analog Devices, AD9739A Datasheet - Page 56

• Manufacturer Part Number: AD9739A
• Description: 14-Bit, 2.5 GSPS, RF D/A Converter
• Manufacturer: Analog Devices

Specifications of AD9739A

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): n/a
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9737A/AD9739A
CLOCK INPUT CONSIDERATIONS
The quality of the clock source and its drive strength are important
considerations in maintaining the specified ac performance.
The phase noise and spur characteristics of the clock source
should be selected to meet the target application requirements.
Phase noise and spurs at a given frequency offset on the clock
source are directly translated to the output signal. It can be shown
that the phase noise characteristics of a reconstructed output
sine wave are related to the clock source by 20 × log10(f
when the DAC clock path contribution, along with thermal and
quantization effects, are negligible.
The
performance when driven by a fast slew rate originating from
the LVPECL or CML output drivers. For a low jitter sinusoidal
clock source, the
and provide a CML input signal for the
clock receiver. Note that all specifications and characterization
presented in the data sheet are with the
high quality RF signal generator with the clock receiver biased at
an 800 mV level.
AD9737A/AD9739A
ADCLK914
FREF
clock receiver provides optimum jitter
can be used to square-up the signal
50Ω
50Ω
PLL
Figure 173.
10nF
10nF
AD9737A/AD9739A
ADCLK914
Figure 174.
ADF4350
D
D
VCO
V
V
REF
T
ADCLK914
ADF4350
50Ω
driven by a
DIV-BY-2
N = 0 – 4
OUT
50Ω
/f
Interface to the
Interface to the
CLK
Rev. | Page 56 of 64
N
)
V
V
C
CC
EE
V
VCO
ADCLK914
RF
RF
AD9737A/AD9739A
RF
RF
AD9737A/AD9739A
Figure 174 shows a clock source based on the
noise/jitter PLL. The
from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms.
Each single-ended output can provide a squared-up output
level that can be varied from −4 dBm to +5 dBm, allowing for
>2 V p-p output differential swings. The
an additional CML buffer that can be used to drive another
AD9737A/AD9739A
OUT
OUT
OUT
OUT
A+
A–
A+
A–
Q
Q
DACCLK_N
DACCLK_P
Figure 175. Clock Input and Common-Mode Control
50Ω
100Ω
1.8V p-p
CLK Input
CLK Input
AD9737A/AD9739A
50Ω
AD9737A/AD9739A
3.9nH
100Ω
10nF
10nF
1nF
1nF
device.
ADF4350
ESD
IOUT ARRAY
IOUT ARRAY
4-BIT PMOS
4-BIT NMOS
CLKx_OFFSET
CLKx_OFFSET
DACCLK_P
DACCLK_N
DACCLK_P
DACCLK_N
DIR_x = 0
DIR_x = 0
can provide output frequencies
ADF4350
ADF4350
Data Sheet
VDDC
VSSC
also includes
low phase