AD5421 Analog Devices, AD5421 Datasheet - Page 23

• Manufacturer Part Number: AD5421
• Description: 16-Bit, Serial Input, Loop-Powered, 4mA to 20mA DAC
• Manufacturer: Analog Devices

Specifications of AD5421

• Resolution (bits): 16bit
• Dac Settling Time: 50µs
• Max Pos Supply (v): +52V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: SPI

Data Sheet
POWER-ON DEFAULT
The AD5421 powers on with all registers loaded with their default
values and with the loop current in the alarm state set to 3.2 mA
or 22.8 mA/24 mA (depending on the state of the ALARM_
CURRENT_DIRECTION pin and the selected range). The
AD5421 remains in this state until it is programmed with new
values. The SPI watchdog timer is enabled by default with a
timeout period of 1 sec. If there is no communication with the
AD5421 within 1 sec of power-on, the FAULT pin is set.
HART COMMUNICATIONS
The AD5421 can be interfaced to a Highway Addressable
Remote Transducer (HART) modem to enable HART digital
communications over the 2-wire loop connection. Figure 46
shows how the modem frequency shift keying (FSK) output is
connected to the AD5421.
To achieve a 1 mA p-p FSK current signal on the loop, the voltage
at the C
output from the HART modem, this means that the signal must
be attenuated by a factor of 4.5. The following equation can be
used to calculate the values of the C
From this equation, the ratio of C
ratio of the capacitor values sets the amplitude of the HART
FSK signal on the loop. The absolute values of the capacitors set
the response time of the loop current, as well as the bandwidth
presented to the HART signal connected at the C
bandwidth must pass frequencies from 500 Hz to 10 kHz. The
two capacitors and the internal impedance, R
pass filter. The 3 dB frequency of this high-pass filter should be
less than 500 Hz and can be calculated as follows:
4
MODEM
HART_OUT
f
HART
5 .
3
HART_IN
dB
IN
=
Figure 46. Connecting a HART Modem to the AD5421
pin must be 111 mV p-p. Assuming a 500 mV p-p
=
C
C
2
SLEW
HART
×
π
C
×
HART
+
R
AD5421
C
C
DAC
IN
REG
SLEW
C
LOOP–
HART
DRIVE
×
COM
IN
200kΩ
(
1
C
HART
HART
+
HART
C
to C
SLEW
and C
SLEW
)
DAC
SLEW
is 1 to 3.5. This
, form a high-
IN
capacitors.
pin. The
R
V
L
LOOP
Rev. C | Page 23 of 36
To achieve a 500 Hz high-pass 3 dB frequency cutoff, the com-
bined values of C
correct HART signal amplitude on the current loop, the final
values for the capacitors are C
Output Noise During Silence and Analog Rate of Change
The AD5421 has a direct influence on two important specifi-
cations relating to the HART communications protocol: output
noise during silence and analog rate of change. Figure 24 shows
the measurement of the AD5421 output noise in the HART
extended bandwidth; the noise measurement is 0.2 mV rms,
within the required 2.2 mV rms value.
To meet the analog rate of change specification, the rate of
change of the 4 mA to 20 mA current must be slow enough so
that it does not interfere with the HART digital signaling. This
is determined by forcing a full-scale loop current change
through a 500 Ω load resistor and applying the resulting voltage
signal to the HART digital filter (HCF_TOOL-31). The peak
amplitude of the signal at the filter output must be less than
150 mV. To achieve this, the rate of change of the loop current
must be restricted to less than approximately 1.3 mA/ms.
The output of the AD5421 naturally slews at approximately
880 mA/ms, a rate that is far too great to comply with the
HART specifications. To reduce the slew rate, a capacitor can be
connected from the C
Current Slew Rate Control section. To reduce the slew rate
enough so that the HART specification is met, a capacitor value
in the region of 4.7 µF is required, resulting in a full-scale transition
time of 500 ms. Many applications regard this time as too slow,
in which case the slew rate needs to be digitally controlled by
writing a sequence of codes to the DAC register so that the
output response follows the desired curve.
Figure 47 shows a digitally controlled full-scale step and the
resulting filter output. In Figure 47, it can be seen that the peak
amplitude of the filter output signal is less than the required
150 mV, and the transition time is approximately 30 ms.
Figure 47. Digitally Controlled Full-Scale Step and Resulting HART Digital
12
10
8
6
4
2
0
–50
–30
HART
and C
IN
Filter Output Signal
pin to COM, as described in the Loop
–10
TIME (ms)
SLEW
HART
should be 21 nF. To ensure the
= 4.7 nF and C
10
30
SLEW
AD5421
= 16.3 nF.
50
150
100
50
0
–50
–100
–150