CS44600-CQZ Cirrus Logic Inc, CS44600-CQZ Datasheet - Page 43

• Manufacturer Part Number: CS44600-CQZ
• Description: IC AMP CTLR DGTL 6CH 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Digital Amplifier Controllerr

Specifications of CS44600-CQZ

• Package / Case: 64-LQFP
• Applications: Automotive Systems
• Mounting Type: Surface Mount
• Thd Plus Noise: 0.05 %
• Operating Supply Voltage: 2.5 V
• Supply Current: 150 mA
• Maximum Power Dissipation: 387 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Supply Type: Digital
• Supply Voltage (max): 2.62 V
• Supply Voltage (min): 2.37 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1023 - EVAL BOARD FOR CS44600
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1068-5

DS633F1
5.1.4
Recommended Power-Down Sequence
1. Mute all channel outputs by setting the corresponding CHxx_MUTE bits to ‘1’b.
2. When driving a single-ended (half-bridged) power output stage, set the RAMP[1:0] bits to ‘01’b and
3. Power down each channel’s PWM modulator by setting the PDN_PWMxx bit to ‘1’b. If single-ended,
4. The ramp-down function can be configured to cause an interrupt condition when the ramp period has
5. Once the ramp-down sequence has completed, set the appropriate GPIO pin, or other control signal,
6. For full-bridged power output stage configurations, the ramp-down sequence is not required. Powering
7. Concurrently with the ramp-down sequence, if desired, stop all clocks on the DAI interface
8. Set the PDN bit to ‘1’b to put the CS44600 in the power down state.
the required ramp speed, to initiate a ramp cycle when the channel is powered down.
this will initiate a sequence which will slowly decrease the DC voltage, from Vpower÷2 to 0 V, across
the AC-coupling capacitor.
completed. This will be indicated by an active INT signal.
to power down the power output stage.
down the power output stage will not cause an audible pop from the speaker.
(DAI_MCLK, DAI_SCLK, DAI_LRCK).
Done
Y
Read DEC_OUTD[23:0]
Set PSR_RESET = 1b
Figure 30. PSR Calibration Sequence
DEC_OUTD[23:0] <
Set PSR_EN = 1b
Set PSR_EN = 0b
C
PSR
3FEF90h <
400FFFh?
=C
PSR
- 9Bh
Y
N
DEC_OUTD[23:0] >
400FFFh?
N
C
PSR
=C
PSR
+ 9Bh
CS44600
43