AD5024 Analog Devices, AD5024 Datasheet
AD5024
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AD5024 Summary of contents
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... The AD5024/AD5044/AD5064/AD5064-1 incorporate a power-on reset circuit that ensures the DAC output powers up to zero scale or midscale and remains there until a valid write takes place to the device. The AD5024/AD5044/ AD5064/AD5064-1 contain a power-down feature that reduces the current consumption of the device to typically 400 and provides software selectable output loads while in power- down mode. Total unadjusted error for the parts is < ...
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... Power Supply Bypassing and Grounding................................ 24 Microprocessor Interfacing....................................................... 25 Applications Information .............................................................. 26 Using a Reference as a Power Supply....................................... 26 Bipolar Operation....................................................................... 26 Using the AD5024/AD5044/AD5064/AD5064-1 with a Galvanically Isolated Interface ................................................. 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 28 Changes to Figure 4...........................................................................6 Added Figure 6...................................................................................8 Added Table 6 ...
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... Max Bits AD5064/AD5064-1 Bits AD5044 Bits AD5024 ±4 LSB AD5064/AD5064- +105°C ±4 LSB AD5064/AD5064- +125°C LSB AD5044 LSB AD5024 ±1 LSB ± 2 5.5 V REF DD ±1.8 mV μV/°C ±0.07 % FSR All 1s loaded to DAC register, V ±0.05 % FSR < ...
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... AD5024: Code 32 to Code 4064. Output unloaded. 4 See the Terminology section. 5 Offset error calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output unloaded 6 Guaranteed by design and characterization; not production tested. ...
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... Daisy-chain mode only. 3 Measured with the load circuit of Figure 3. t determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32 Circuit and Timing Diagrams = 1 ns/V (10 and timed from a voltage level unless otherwise noted ...
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... AD5024/AD5044/AD5064 SCLK t 8 SYNC DIN DB31 1 LDAC 2 LDAC CLR V OUT 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. SCLK SYNC DIN DB31 INPUT WORD FOR DAC N SDO 1 LDAC CLR DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY ...
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... Exposure to absolute + 0 maximum rating conditions for extended periods may affect + 0 device reliability ESD CAUTION − T )/θ J MAX A JA Rev Page AD5024/AD5044/AD5064 ...
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... AD5024/AD5044/AD5064 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC LDAC can be operated in two modes, asynchronously and synchronously, as shown in this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode. When daisy-chain mode is enabled, this pin cannot be tied permanently low ...
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... REF OUT REF TOP VIEW (Not to Scale REF OUT CLR OUT POR REF Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration Rev Page AD5024/AD5044/AD5064 Figure 4 . Pulsing nd falling edge, the rising edge of powers up the DD ...
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... DAC CODE Figure 11. AD5064/AD5064-1 DNL 4.096V REF T = 25° 4096 8192 12,288 DAC CODE Figure 12. AD5044 DNL 4.096V REF T = 25° 4096 8192 12,288 DAC CODE Figure 13. AD5024 DNL 65,024 16,384 16,384 ...
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... Rev Page AD5024/AD5044/AD5064 T = 25°C A MAX TUE @ V = 5.5V DD MIN TUE @ V = 5.5V DD 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) Figure 17. TUE vs. Reference Input Voltage DAC A DAC B DAC D DAC 5. 4.096V REF – ...
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... AD5024/AD5044/AD5064 0 4.096V REF T = 25°C A 0.1 GAIN ERROR 0 FULL-SCALE ERROR –0.1 –0.2 4.50 4.75 5.00 V (V) DD Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage 0. 4.096V REF T = 25°C A 0.09 0.06 0.03 0 4.50 4.75 5.00 V (V) DD Figure 21. Offset Error Voltage vs. Supply Voltage 40 MEAN: 4.11699 SD: 0.0544403 35 LIMITS: LOW: 3 HIGH: 4.3 CPk: LOW: 6.84 HIGH: 1. ...
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... CH2 = CH1 DAC A –1 –2 –3 0 2.52V Rev Page AD5024/AD5044/AD5064 = 4.096V V DD DAC A CH3 2V M2ms A CH1 2.52V T 20.4% Figure 29. Power-On Reset to Midscale OUT DD POWER-UP TO MIDSCALE OUTPUT UNLOADED CH2 500mV M2µs A CH2 T 55% Figure 30 ...
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... AD5024/AD5044/AD5064 5V 4.096V DD REF 25º –1 –2 –3 –4 0 2.5 5.0 TIME (μs) Figure 32. Analog Crosstalk –1 –2 –3 –4 0 2.5 5.0 TIME (μs) Figure 33. DAC-to-DAC Crosstalk 4.096V DD REF T = 25ºC A DAC LOADED WITH MIDSCALE 4s/DIV Figure 34 ...
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... CH1 Figure 42. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale CH1 Figure 43. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, Rev Page AD5024/AD5044/AD5064 CODE = MIDSCALE 4.096V DD REF –20 –15 –10 – ...
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... AD5024/AD5044/AD5064 V = 5V,V = 4.096V DD REF T = 25°C A CH1 20mV CH2 5V M4µs T 8.6% Figure 44. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No Load DAC A 129mV p-p SCLK A CH2 1.2V Figure 45. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, Rev Page 25° 5V ...
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... OUT OUT region of the transfer function. Offset error is calculated using a reduced code range—AD5064/AD5604-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064, with output unloaded. Offset error can be negative or positive and is expressed in millivolts. Gain Error Gain error is a measure of the span error of the DAC ...
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... AD5024/AD5044/AD5064 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC ...
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... DAC address bits (see Table 9), and finally the bit data-word. The data-word comprises 12-bit, 14-bit, or 16-bit input code, followed by eight, six, or four don’t care bits for the AD5024, AD5044, and AD5064/AD5064-1, respectively (see Figure 47, Figure 48, and Figure 49). These data bits are transferred to the DAC register on the 32 executed on individually selected DAC channels or on all DACs ...
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... DB31 INVALID WRITE SEQUENCE: ND SYNC HIGH BEFORE 32 FALLING EDGE D11 D10 DATA BITS Figure 47. AD5024 Shift Register Content D13 D12 D11 D10 DATA BITS Figure 48. AD5044 Shift Register Content D15 D14 D13 D12 D11 D10 D9 Figure 49 ...
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... DIN line is clocked into the 32-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5024/AD5044/AD5064/AD5064-1 compatible with high speed DSPs. On the 32 the last data bit is clocked in and the programmed function is executed, that is, an LDAC -dependent change in DAC register contents and/or a change in the mode of operation ...
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... Table 8). Any events on LDAC or CLR during power-on reset are ignored. The power-on reset circuit is triggered when V passes 2.6 V approximately and DD takes 50 μs to complete. No writes to the AD5024/AD5044/ AD5064/AD5064-1 should take place during this time. For applications which have a slow V ramp time (for example, DD ...
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... CLEAR CODE REGISTER The AD5024/AD5044/AD5064/AD5064-1 have a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers to the data contained in the user-configurable CLR register and sets the ...
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... POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board (PCB) containing the AD5024/AD5044/ AD5064/AD5064-1 should have separate analog and digital sections. If the AD5024/AD5044/AD5064/AD5064-1 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only ...
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... Figure 52. AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-BF53x Interface AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface Figure 53 shows a serial interface between the AD5024/AD5044/ AD5064/AD5064-1 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5024/ AD5044/AD5064/AD5064-1, and the MOSI output drives the serial data line of the DAC. 68HC11/68L11* AD5024/ AD5044/ ...
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... ADuM1300 three-channel digital isolator provides the required isolation (see Figure 58). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer regulator provides the 5 V supply required for the AD5024/ AD5044/AD5064/AD5064-1. POWER or an ...
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... Figure 59. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8° 0.30 0.65 0° 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 60. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev Page AD5024/AD5044/AD5064 0.75 0.60 0.45 0.75 0.60 0.45 ...
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... AD5044BRUZ −40°C to +125°C AD5044BRUZ-REEL7 −40°C to +125°C AD5024BRUZ −40°C to +125°C AD5024BRUZ-REEL7 −40°C to +125°C EVAL-AD5064-1EBZ EVAL-AD5064EBZ RoHS Compliant Part. ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...