AD5024 Analog Devices, AD5024 Datasheet - Page 23

• Manufacturer Part Number: AD5024
• Manufacturer: Analog Devices

Specifications of AD5024

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

CLEAR CODE REGISTER
The AD5024/AD5044/AD5064/AD5064-1 have a hardware
CLR pin that is an asynchronous clear input. The CLR input is
falling edge sensitive. Bringing the CLR line low clears the
contents of the input register and the DAC registers to the data
contained in the user-configurable CLR register and sets the
analog outputs accordingly (see
used in system calibration or reset to load zero scale, midscale,
or full scale to all channels together. Note that zero scale and full
scale are outside the linear region of the DAC. These clear code
values are user-programmable by setting two bits, Bit DB1 and
Bit DB0, in the shift register (see
clears the outputs to 0 V. Command 0101 is designated for
loading the clear code register (see
Table 14. Clear Code Register
DB1 (CR1)
0
0
1
1
The part exits clear code mode on the 32
next write to the part. If hardware CLR pin is activated during a
write sequence, the write is aborted.
The CLR pulse activation time, which is the falling edge of CLR
to when the output starts to change, is typically 10.6 μs. See
Table 16
code register.
LDAC FUNCTION
Hardware LDAC Pin
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin, as shown in
permanently low or pulsed. There are two methods of using the
hardware LDAC pin, synchronously and asynchronously.
Table 16. 32-Bit Shift Register Contents for Clear Code Function
MSB
DB31 to DB28
X
Don’t cares
Table 17. 32-Bit Shift Register Contents for LDAC Overwrite Function
MSB
DB31 to
DB28
X
Don’t
cares
for contents of the shift register while loading the clear
DB27
0
Command bits (C3 to C0)
DB27
0
DB0 (CR0)
0
1
0
1
DB26
1
Command bits (C3 to C0)
DB26
1
DB25
1
Table 14
Table 14
Table 8
Figure 4 LDAC can be
DB25
0
DB24
0
Clears to Code
0x0000
0x8000
0xFFFF
No operation
). This function can be
nd
). The default setting
).
falling edge of the
.
DB24
1
DB23
X
Address bits (A3 to A0)—
DB23
X
DB22
X
don’t cares
Rev. E | Page 23 of 28
Address bits (A3 to A0)
DB21
X
DB22
X
Synchronous LDAC : After new data is read, the DAC registers
are updated on the falling edge of the 32
LDAC is held low.
Asynchronous LDAC : The outputs are not updated at the same
time that the input registers are written to. When LDAC is
pulsed low, the DAC registers are updated with the contents of
the input registers.
Software LDAC Function
Alternatively, the outputs of all DACs can be updated simulta-
neously or individually using the software LDAC function by
writing to Input Register n and updating all DAC registers.
Command 0010 is reserved for this software LDAC function.
Writing to the DAC using Command 0110 loads the 4-bit
LDAC register (DB3 to DB0). The default for each channel
is 0; that is, the LDAC pin works normally. Setting the bits to 1
updates the DAC channel regardless of the state of the hardware
LDAC pin, so that it effectively sees the hardware LDAC pin as
being tied low (see
operation.) This flexibility is useful in applications where the
user wants to simultaneously update select channels while the
remainder of the channels are synchronously updating.
Table 15. LDAC Overwrite Definition
LDAC Bits
(DB3 to DB0)
0
1
1
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see
bits (DB0 to DB3) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware LDAC pin.
X = don’t care.
DB20
X
Load LDAC Register
X
DB21
DB19
to DB4
X
Don’t
cares
DB20
X
LDAC Pin
1 or 0
X
1
Table 15
DB3
DAC D
Setting LDAC bits to 1 overrides LDAC pin
AD5024/AD5044/AD5064
DB19 to DB2
X
Don’t cares
for the
LDAC Operation
Determined by the LDAC pin.
DAC channels update, overrides
the LDAC pin. DAC channels see
LDAC as 0.
DB2
DAC C
Table 17
LDAC register mode of
nd
SCLK pulse, provided
). Setting the
1/0
DB1
Clear code register
DB1
DAC B
(CR1 to CR0)
LSB
DB0
1/0
LDAC
LSB
DB0
DAC A