AD5724 Analog Devices, AD5724 Datasheet - Page 9

• Manufacturer Part Number: AD5724
• Description: Complete, Quad, 12-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs
• Manufacturer: Analog Devices

Specifications of AD5724

• Resolution (bits): 12bit
• Dac Update Rate: 100kSPS
• Dac Settling Time: 8.5µs
• Max Pos Supply (v): +16.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2, 6, 12, 13
3
4
5
7
8
9
10
11
14
15
16
17
18, 19
20, 21
22
23
24
Exposed
Paddle
Mnemonic
AV
NC
V
V
BIN/2sCOMP
SYNC
SCLK
SDIN
LDAC
CLR
DV
GND
SDO
REFIN
DAC_GND
SIG_GND
V
V
AV
AV
OUT
OUT
OUT
OUT
SS
DD
SS
CC
A
B
D
C
Description
Negative Analog Supply. Voltage ranges from −4.5 V to −16.5 V. This pin can be connected to 0 V if output
ranges are unipolar.
Do not connect to these pins.
Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Determines the DAC coding for a bipolar output range. This pin should be hardwired to either DV
When hardwired to DV
complement. (For unipolar output ranges, coding is always straight binary).
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Load DAC, Logic Input. This is used to update the DAC registers and consequently, the analog outputs. When
this pin is tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is
held high during the write cycle, the DAC input register is updated, but the output update is held off until the
falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of
LDAC. The LDAC pin should not be left unconnected.
Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user-selectable).
Digital Supply. Voltage ranges from 2.7 V to 5.5 V.
Ground Reference.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
External Reference Voltage Input. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance.
Ground Reference for the Four Digital-to-Analog Converters.
Ground Reference for the Four Output Amplifiers.
Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V.
This exposed paddle should be connected to the potential of the AV
unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal
performance.
NOTES
1. NC = NO CONNECT.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
THERMALLY CONNECTED TO A COPPER PLANE
FOR ENHANCED THERMAL PERFORMANCE.
BIN/2sCOMP
CC
, input coding is offset binary. When hardwired to GND, input coding is twos
V
V
SYNC
SCLK
LDAC
AV
OUT
OUT
SDIN
CLR
NC
NC
NC
Figure 5. Pin Configuration
SS
A
B
Rev. D | Page 9 of 32
10
11
12
1
2
3
4
5
6
7
8
9
(Not to Scale)
AD5724/
AD5734/
AD5754
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
V
V
AV
SIG_GND
SIG_GND
REFIN
SDO
GND
DV
DAC_GND
DAC_GND
NC
OUT
OUT
DD
CC
C
D
SS
pin, or alternatively, it can be left electrically
AD5724/AD5734/AD5754
CC
or GND.