AD5754 Analog Devices, AD5754 Datasheet - Page 19

• Manufacturer Part Number: AD5754
• Description: Complete, Quad, 16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5754

• Resolution (bits): 16bit
• Dac Update Rate: 100kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +16.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
only if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If
SYNC is brought high before the 24
data written is invalid. If more than 24 falling SCLK edges are
applied before SYNC is brought high, the input data is also
invalid. The input register addressed is updated on the rising
edge of SYNC . For another serial transfer to take place, SYNC
must be brought low again. After the end of the serial data
transfer, data is automatically transferred from the input shift
register to the addressed register.
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low while SYNC is high.
*
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Daisy Chaining the AD5724/AD5734/AD5754
68HC11
MISO
MOSI
*
SCK
PC7
PC6
th
falling SCLK edge, the
SDIN
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
AD5754*
AD5754*
AD5754*
AD5724/
AD5734/
AD5724/
AD5734/
AD5724/
AD5734/
SDIN
SDO
SDIN
SDO
SDO
Rev. D | Page 19 of 32
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
of serial interface lines. The first falling edge of SYNC starts the
write cycle. SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the SDIN input of the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24 × N, where N is the total number of
AD5724/AD5734/AD5754 devices in the chain. When the serial
transfer to all devices is complete, SYNC is taken high. This
latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input shift
register. The serial clock can be a continuous or a gated clock.
A continuous SCLK source can only be used if SYNC is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to
latch the data.
Readback Operation
Readback mode is invoked by setting the R/ W bit = 1 in the
serial input shift register write. (If the SDO output is disabled
via the SDO disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again). With R/ W = 1, Bit A2 to Bit A0 in association
with Bit REG2 to Bit REG0, select the register to be read. The
remaining data bits in the write sequence are don’t care bits.
During the next SPI write, the data appearing on the SDO
output contains the data from the previously addressed register.
For a read of a single register, the NOP command can be used
in clocking out the data from the selected register on SDO. The
readback diagram in
example, to read back the DAC register of Channel A, the
following sequence should be implemented:
1.
2.
Write 0x800000 to the AD5724/AD5734/AD5754 input
register. This configures the part for read mode with the
DAC register of Channel A selected. Note that all the data
bits, DB15 to DB0, are don’t care bits.
Follow this with a second write, a NOP condition, 0x180000.
During this write, the data from the register is clocked out
on the SDO line.
Figure 4
AD5724/AD5734/AD5754
shows the readback sequence. For