AD5754 Analog Devices, AD5754 Datasheet - Page 20

• Manufacturer Part Number: AD5754
• Description: Complete, Quad, 16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5754

• Resolution (bits): 16bit
• Dac Update Rate: 100kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +16.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5724/AD5734/AD5754
LOAD DAC (LDAC)
After data has been transferred into the input register of the
DACs, there are two ways to update the DAC registers and DAC
outputs. Depending on the status of both SYNC and LDAC , one
of two update modes is selected: individual DAC updating or
simultaneous updating of all DACs.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the input shift register. The addressed DAC output is updated
on the rising edge of SYNC .
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the input shift register. All DAC outputs are asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC .
ASYNCHRONOUS CLEAR (CLR)
CLR is an active low clear that allows the outputs to be cleared
to either zero-scale code or midscale code. The clear code value is
user-selectable via the CLR select bit of the control register (see
the
for a minimum amount of time to complete the operation (see
Figure 2
remains at the cleared value until a new value is programmed.
The outputs cannot be updated with a new value while the CLR
pin is low. A clear operation can also be performed via the clear
command in the control register.
CONFIGURING THE AD5724/AD5734/AD5754
When the power supplies are applied to the AD5724/AD5734/
AD5754, the power-on reset circuit ensures that all registers
default to 0. This places all channels in power-down mode. The
Figure 41. Simplified Diagram of Input Loading Circuitry for One DAC
Control Register
). When the
REFIN
LDAC
SYNC
SCLK
SDIN
CLR signal is returned high, the output
section). It is necessary to maintain
12-/14-/16-BIT
INTERFACE
REGISTER
REGISTER
LOGIC
INPUT
DAC
DAC
AMPLIFIER
OUTPUT
SDO
V
OUT
CLR low
Rev. D | Page 20 of 32
DV
are powered. If this is not done, the first write to the device may
be ignored. The first communication to the AD5724/AD5734/
AD5754 should be to set the required output range on all
channels (the default range is the 5 V unipolar range) by writing
to the output range select register. The user should then write to
the power control register to power on the required channels. To
program an output value on a channel, that channel must first
be powered up; any writes to a channel while it is in power-down
mode are ignored. The AD5724/ AD5734/AD5754 operate with a
wide power supply range. It is important that the power supply
applied to the parts provides adequate headroom to support the
chosen output ranges.
TRANSFER FUNCTION
Table 7 to Table 15 show the relationships of the ideal input code
to output voltage for the AD5754, AD5734, and AD5724, respec-
tively, for all output voltage ranges. For unipolar output ranges,
the data coding is straight binary. For bipolar output ranges, the
data coding is user-selectable via the BIN/ 2sCOMP pin and can
be either offset binary or twos complement.
For a unipolar output range, the output voltage expression is
given by
For a bipolar output range, the output voltage expression is given by
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
V
Gain is an internal gain whose value depends on the output
range selected by the user, as shown in Table 6.
Table 6. Internal Gain Values
Output Range (V)
+5
+10
+10.8
±5
±10
±10.8
REFIN
CC
V
V
should be brought high before any of the interface lines
is the reference voltage applied at the REFIN pin.
OUT
OUT
=
=
V
V
REFIN
REFIN
×
×
Gain
Gain
⎡
⎢ ⎣
⎡
⎢ ⎣
2
2
D
D
N
N
⎤
⎥ ⎦
⎤
⎥ ⎦
−
Gain
Gain Value
2
4
4.32
4
8
8.64
×
2
V
REFIN