CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 63

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

DS245F4
13.4
Hardware Mode 3 Description
(Transceive Data Flow, with SRC)
Hardware Mode 3 data flow is shown in
verted. The audio data at the new rate is then output via the serial audio output port. Different audio data,
synchronous to OMCK, may be input into the serial audio input port, and output via the AES3 transmitter.
The channel status data, user data, and validity bit information are handled in two alternative modes: 3A
and 3B, determined by a start-up resistor on the COPY pin. In mode 3A, the received PRO, COPY, ORIG,
and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied from the
received channel status data, and the transmitted U and V bits are zero.
In mode 3B, only the COPY, and ORIG pins are output, and reflect the received channel status data. The
transmitted channel status bits, user data, and validity bits are input serially via the PRO/C, EMPH/U, and
AUDIO/V pins.
The serial audio input port is always a slave.
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held.
Start-up options are shown in
whether TCBL is an input or an output, the serial audio ports formats, and the source of the transmitted C,
U, and V data. The following pages contain the detailed pin descriptions for Hardware mode 3.
RXP
RXN
Figure 20
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
RMCK RERR
VD+
Figure 26. Hardware Mode 3 - Transceive Data Flow, with SRC
DFC0
Clocked by
Input Derived Clock
AES3 Rx
&
Decoder
shows the timing requirements.
DFC1
Table
VD+
Sample
Rate
Converter
H/S
12, and allow choice of the serial audio output port as a master or slave,
Clocked by
Output Clock
Figure
PRO/C
SDOUT
OSCLK
Serial
Audio
Output
26. Audio data is input via the AES3 receiver, and rate con-
COPY ORIG EMPH/U AUDIO/V TCBL
OLRCK
C & U bit Data Buffer
ILRCK
ISCLK
Serial
Audio
Input
SDIN
AES3
Encoder
& Tx
Output
Clock
Source
OMCK
TXP
TXN
CS8420
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