CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 9

IC SAMPLE RATE CONVERTER 28SOIC

CS8420-CSZ

Manufacturer Part Number
CS8420-CSZ
Description
IC SAMPLE RATE CONVERTER 28SOIC
Manufacturer
Cirrus Logic Inc
Type
Sample Rate Converterr
Datasheets

Specifications of CS8420-CSZ

Package / Case
28-SOIC
Applications
CD-R, DAT, DVD, MD, VTR
Mounting Type
Surface Mount
Operating Supply Voltage
5 V
Operating Temperature Range
- 10 C to + 70 C
Mounting Style
SMD/SMT
Resolution
17 bit to 24 bit
Control Interface
3 Wire, Serial
Supply Voltage Range
4.75V To 5.25V
Audio Ic Case Style
SOIC
No. Of Pins
28
Bandwidth
20kHz
Rohs Compliant
Yes
Audio Control Type
Volume
Dc
0841
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1782 - EVALUATION BOARD FOR CS8420
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1125-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS8420-CSZ
Manufacturer:
CIRRUS
Quantity:
319
Part Number:
CS8420-CSZ
Manufacturer:
CIRRUS
Quantity:
9 908
Part Number:
CS8420-CSZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS8420-CSZ/D1
Manufacturer:
CIRRUS
Quantity:
378
Part Number:
CS8420-CSZR
Manufacturer:
NICHICON
Quantity:
4 200
DS245F4
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; C
OSCLK Active Edge to SDOUT Output Valid
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
O/RMCK to I/OSCLK active edge delay
O/RMCK to I/OLRCK delay
I/OSCLK and I/OLRCK Duty Cycle
Slave Mode
I/OSCLK Period
I/OSCLK Input Low Width
I/OSCLK Input High Width
I/OSCLK Active Edge to I/OLRCK Edge
I/OLRCK Edge Setup Before I/OSCLK Active Edge
OSCLK
(output)
O LRCK
(output)
(output)
(output)
O M CK
ISCLK
ILRCK
RM CK
RM CK
(input)
7. The active edges of ISCLK and OSCLK are programmable.
8. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising edge.
9. The polarity of ILRCK and OLRCK is programmable.
10. No more than 128 SCLK per frame.
11. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
12. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.
Figure 1. Audio Port Master Mode Timing
When these signals are derived from RMCK, they are clocked from its falling edge.
has changed.
Hardware M ode
Software M ode
t sm d
Parameter
t
lm d
L
= 20 pF.
(Note 7, 9, 12)
(Note 7, 9, 11)
(Note 7, 8)
(Note 10)
(Note 7)
(Note 7)
(Note 7)
(Note 9)
OLRCK
OSCLK
SDOUT
ILRCK
ISCLK
(input)
(input)
SDIN
Figure 2. Audio Port Slave Mode and Data Input Timing
Symbol
t
t
t
t
t
t
t
t
sckw
sckh
lrckd
lrcks
smd
t
t
sckl
dpd
lmd
t lrckd
dh
ds
Min
20
20
36
14
14
20
20
t
0
0
-
-
lrcks
t
ds
Typ
50
-
-
-
-
-
-
-
-
-
-
t sckh
t
dh
Max
25
16
17
-
-
-
-
-
-
-
-
t sckw
t sckl
CS8420
t dpd
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
9

Related parts for CS8420-CSZ