AD5060 Analog Devices, AD5060 Datasheet - Page 18

• Manufacturer Part Number: AD5060
• Manufacturer: Analog Devices

Specifications of AD5060

• Resolution (bits): 16bit
• Dac Update Rate: 250kSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5040/AD5060
AD5040/AD5060 to Blackfin® ADSP-BF53x Interface
Figure 47 shows a serial interface between the AD5040/
AD5060 and the Blackfin ADSP-53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5040/AD5060, the setup for the interface is: DT0PRI
drives the SDIN pin of the AD5040/AD5060, while TSCLK0
drives the SCLK of the part; the SYNC is driven from TFS0.
AD5040/AD5060 to 80C51/80L51 Interface
Figure 48 shows a serial interface between the AD5060/
AD5040 and the 80C51/80L51 microcontroller. The setup
for the interface is: TxD of the 80C51/80L51 drives SCLK of
the AD5040/AD5060 while RxD drives the serial data line
of the part. The SYNC signal is again derived from a bit-
programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5040, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus only 8 falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data in a
format which has the LSB first. The AD5040/AD5060 require
data to be received with the MSB as the first bit. The
80C51/80L51 transmit routine should take this into account.
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
ADSP-BF53x
80C51/80L51
Figure 47. AD5040/AD5060 to Blackfin® ADSP-BF53x Interface
Figure 48. AD5040/AD5060 to 80C51/80L51 Interface
TSCLK0
DT0PRI
1
1
TFS0
P3.3
RxD
TxD
DIN
SCLK
SYNC
SYNC
SCLK
DIN
AD5060
AD5040/
AD5040/
AD5060
1
1
Rev. A | Page 18 of 24
AD5040/AD5060 to MICROWIRE Interface
Figure 49 shows an interface between the AD5040/AD5060 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and is clocked into the
AD5040/AD5060 on the rising edge of the SK.
1
ADDITIONAL PINS OMITTED FOR CLARITY
MICROWIRE
Figure 49. AD5040/AD5060 to MICROWIRE Interface
1
CS
SK
SO
SYNC
SCLK
DIN
AD5040/
AD5060
1