AD5622 Analog Devices, AD5622 Datasheet

no-image

AD5622

Manufacturer Part Number
AD5622
Description
2.7 V to 5.5 V,
Manufacturer
Analog Devices
Datasheet

Specifications of AD5622

Resolution (bits)
12bit
Dac Update Rate
1.7MSPS
Dac Settling Time
6µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
I2C/Ser 2-wire,Ser

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5622AKSZ-2500RL7
Manufacturer:
AD
Quantity:
3 400
Part Number:
AD5622AKSZ-2REEL7
Manufacturer:
VISHAY
Quantity:
11 159
Part Number:
AD5622AKSZ-2SMD7
Manufacturer:
TI
Quantity:
2 000
Part Number:
AD5622BKSZ-2REEL7
Manufacturer:
ADI
Quantity:
3 626
Part Number:
AD5622BKSZ-2REEL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD5622YKSZ-1500RL7
Manufacturer:
ADI
Quantity:
6 926
FEATURES
Single 8-, 10-, 12-bit DACs, 2 LSB INL
6-lead SC70 package
Micropower operation: 100 μA max @ 5 V
Power-down to <150 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
I
On-chip output buffer amplifier, rail-to-rail operation
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5602/AD5612/AD5622, members of the nanoDAC
family, are single 8-, 10-, 12-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply, consuming <100 μA
at 5 V. These DACs come in tiny SC70 packages. Each DAC
contains an on-chip precision output amplifier that allows rail-
to-rail output swing to be achieved.
The AD5602/AD5612/AD5622 use a 2-wire I
serial interface that operates in standard (100 kHz), fast
(400 kHz), and high speed (3.4 MHz) modes.
The references for AD5602/AD5612/AD5622 are derived from
the power supply inputs to give the widest dynamic output range.
Each part incorporates a power-on reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place to the device. The parts contain a power-down
feature that reduces the current consumption of the devices to
<150 nA at 3 V and provides software-selectable output loads
while in power-down mode. The parts are put into power-down
mode over the serial interface. The low power consumption of
the AD5602/AD5612/AD5622 in normal operation makes them
ideally suited for use in portable battery-operated equipment. The
typical power consumption is 0.4 mW at 5 V.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2
C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
2
C-compatible
2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDACs
I
2
C
®
-Compatible Interface, Tiny SC70 Package
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Table 1. Related Devices
Part No.
AD5601/AD5611/AD5621
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.
ADDR
Available in a 6-lead SC70 package.
Maximum 100 μA power consumption, single-supply
operation. These parts operate from a single 2.7 V to 5.5 V
supply, typically consuming 0.2 mW at 3 V and 0.4 mW at
5 V, making them ideal for battery-powered applications.
The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/μs.
Reference derived from the power supply.
Standard, fast, and high speed mode I
Designed for very low power consumption.
Power-down capability. When powered down, the DAC
typically consumes <150 nA at 3 V.
Power-on reset and brownout detection.
CONTROL
POWER-ON
LOGIC
INPUT
REGISTER
RESET
SCL
DAC
AD5602/AD5612/AD5622
FUNCTIONAL BLOCK DIAGRAM
SDA
REF(+)
8-/10-/12-BIT
V
DD
DAC
©2006 Analog Devices, Inc. All rights reserved.
CONTROL LOGIC
POWER-DOWN
GND
Description
2.7 V to 5.5 V, <100 μA, 8-, 10-, 12-bit
nanoDAC with SPI® interface in a
tiny SC70 package
Figure 1.
AD5602/AD5612/AD5622
OUTPUT
BUFFER
2
C interface.
NETWORK
RESISTOR
www.analog.com
®
with
V
OUT

Related parts for AD5622

AD5622 Summary of contents

Page 1

... V and provides software-selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface. The low power consumption of the AD5602/AD5612/AD5622 in normal operation makes them ideally suited for use in portable battery-operated equipment. The typical power consumption is 0 ...

Page 2

... AD5602/AD5612/AD5622 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... Timing Specifications............................................................ 4 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 D/A Section................................................................................. 15 REVISION HISTORY 3/06—Rev Rev. B Changes to Table 2 ...

Page 3

... 0.4 V 0.6 V ±1 μ Rev Page AD5602/AD5612/AD5622 unless otherwise noted. MIN MAX Test Conditions/Comments DAC output unloaded B, Y versions B, Y versions A version B, Y versions A, W versions Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Code ¼ ...

Page 4

... AD5602/AD5612/AD5622 Parameter POWER REQUIREMENTS (Normal Mode (All Power-Down Modes POWER EFFICIENCY I /I OUT DD 1 Temperature ranges for A, B versions: −40°C to +125°C, typical at 25°C. 2 Linearity calculated using a reduced code range 64 to 4032. ...

Page 5

... Fast mode SP High speed mode 1 See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622- refers to the capacitance on the bus line The SDA and SCL timing is measured with the input filters enabled ...

Page 6

... AD5602/AD5612/AD5622 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter V to GND DD Digital Input Voltage to GND V to GND OUT Operating Temperature Range Extended Automotive (W, Y Versions) Extended Industrial (A, B Versions) Storage Temperature Range Maximum Junction Temperature SC70 Package θ Thermal Impedance JA θ ...

Page 7

... V Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. OUT ADDR OUT AD5602/ AD5612/ AD5622 SCL GND 2 5 TOP VIEW (Not to Scale) SDA Figure 3. Pin Configuration Rev Page AD5602/AD5612/AD5622 should be decoupled to GND. DD ...

Page 8

... Figure 4. Typical AD5622 Integral Nonlinearity Error 0. 25°C A 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 0 500 1000 1500 2000 2500 DAC CODE Figure 5. Typical AD5622 Differential Nonlinearity Error 0. 0. 25°C A 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 0 200 400 600 DAC CODE Figure 6 ...

Page 9

... Figure 14. AD5622 INL Error vs. Temperature (3 V/5 V Supply MIN TUE = MIN TUE = 3V 0 –40 5.2 Figure 15. AD5622 Total Unadjusted Error vs. Temperature (3 V/5 V Supply) Rev Page AD5602/AD5612/AD5622 MAX DNL MIN DNL 3.2 3.7 4.2 4.7 5.2 V (V) DD Figure 13. AD5622 DNL Error vs. Supply MAX INL = 5V ...

Page 10

... MAX DNL = 3V 0.1 0 MIN DNL = 5V –0.1 –0.2 MIN DNL = 3V –0.3 –40 – TEMPERATURE (°C) Figure 16. AD5622 DNL Error vs. Temperature (3 V/5 V Supply) 4 ZERO CODE ERROR = 3V 2 ZERO CODE ERROR = 5V 0 –2 –4 FULL-SCALE ERROR = 3V –6 –8 FULL-SCALE ERROR = 5V –10 –40 –20 ...

Page 11

... 100 120 140 0 25°C A 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –15 CH1 CH2 4.0 4.5 5.0 Rev Page AD5602/AD5612/AD5622 = GND V = GND 25° 25° (µA) DD Figure 25. I Histogram (3 V/5 V Supply 25°C ...

Page 12

... AD5602/AD5612/AD5622 CH1 CH2 CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2µs/DIV Figure 28. Exiting Power-Down Mode CH1 CH2 CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2µs/DIV Figure 29. Full-Scale Settling Time CH1 CH2 CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2µs/DIV Figure 30. Half-Scale Settling Time ...

Page 13

... 25°C A MIDSCALE LOADED CH1 CH1 = 5µV/DIV Figure 34. 1/f Noise, 0 Bandwidth AD5602/AD5612/AD5622 700 25°C A 600 UNLOADED OUTPUT 500 400 ZERO SCALE 300 MIDSCALE 200 100 0 100 1000 Figure 35. Output Noise Spectral Density Rev Page FULL SCALE ...

Page 14

... DAC and output amplifier measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should The zero-code error is always positive in the AD5602/AD5612/AD5622 because the output of the DAC cannot go below 0 V. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 17 ...

Page 15

... D is the decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255 (AD5602 1023 (AD5612 4095 (AD5622 the bit resolution of the DAC. RESISTOR STRING The resistor string structure is shown in Figure 37 simply a string of resistors, each of value R ...

Page 16

... MHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. The AD5602/AD5612/AD5622 each have a 7-bit slave address. The five MSBs are 00011 and the two LSBs are determined by the state of the ADDR pin. The facility to make hardwired changes to ADDR allows the user to incorporate up to three of these devices on one bus as outlined in Table 6 ...

Page 17

... POWER-ON RESET The AD5602/AD5612/AD5622 each contain a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with zeros and the output voltage where it remains until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the DAC output while the process of powering up ...

Page 18

... AD5602/AD5612/AD5622 WRITE OPERATION When writing to the AD5602/AD5612/AD5622, the user must begin with a start command followed by an address byte ( 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. 1 SCL SDA START BY MASTER SERIAL BUS ADDRESS BYTE ...

Page 19

... READ OPERATION When reading data back from the AD5602/AD5612/AD5622, the user begins with a start command followed by an address byte ( 1), after which the DAC acknowledges that SCL SDA START BY MASTER SERIAL BUS ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) 1 SCL ...

Page 20

... When the stop condition is issued, the devices return to standard/fast mode NACK. SR Figure 48. Placing the AD5602/AD5612/AD5622 into High Speed Mode Rev Page HIGH-SPEED MODE R/W ACK. BY ...

Page 21

... AD5612/AD5622 should have separate analog and digital sections, each having its own area of the board. If the AD5602, AD5612, or AD5622 system where other devices require an AGND to DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5602/AD5612/AD5622 ...

Page 22

... AD5602/AD5612/AD5622 OUTLINE DIMENSIONS 2.20 2.00 1.80 2.40 1. 1.25 2.10 1.80 1. PIN 1 0.65 BSC 1.30 BSC 1.00 0.40 1.10 0.90 0.10 0.80 0.70 0.30 0.10 MAX SEATING 0.15 PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 51. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters Rev Page 0.46 0.36 0.22 0.26 0.08 ...

Page 23

... AD5622YKSZ-1REEL7 ±2 LSB 1 AD5622BKSZ-2500RL7 ±2 LSB 1 AD5622BKSZ-2REEL7 ±2 LSB AD5622YKSZ-2500RL7 1 ±2 LSB 1 AD5622YKSZ-2REEL7 ±2 LSB 1 AD5622WKSZ-1500RL7 ±6 LSB 1 AD5622WKSZ-1REEL7 ±6 LSB 1 AD5622AKSZ-2500RL7 ±6 LSB 1 AD5622AKSZ-2REEL7 ±6 LSB Pb-free part Interface Modes Temperature Supported Range Standard, fast and −40°C to +125°C ...

Page 24

... AD5602/AD5612/AD5622 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...

Related keywords