AD5429 Analog Devices, AD5429 Datasheet - Page 23

• Manufacturer Part Number: AD5429
• Description: Dual 8-Bit, High Bandwidth, Multiplying DAC with Serial Interface
• Manufacturer: Analog Devices

Specifications of AD5429

• Resolution (bits): 8bit
• Dac Update Rate: 2.47MSPS
• Dac Settling Time: 30ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

80C51/80L51-to-AD5429/AD5439/AD5449 Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 52. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line, SDIN.
P1.1 is a bit-programmable pin on the serial port and is used to
drive SYNC . When data is to be transmitted to the switch, P1.1
is taken low. The 80C51/80L51 transmit data in 8-bit bytes only;
therefore, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and then a second write cycle is initiated
to transmit the second byte of data. Data on RxD is clocked out
of the microcontroller on the rising edge of TxD and is valid on
the falling edge of TxD. As a result, no glue logic is required
between the DAC and microcontroller interface. P1.1 is taken
high following the completion of this cycle. The 80C51/80L51
provide the LSB of the SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
requirement into account.
MC68HC11-to-AD5429/AD5439/AD5449 Interface
Figure 53 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The SPI on the MC68HC11
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured
by writing to the SPI control register (SPCR); see the MC68HC11
user manual. The SCK of the MC68HC11 drives the SCLK of
the DAC interface; the MOSI output drives the serial data line
(SDIN) of the AD5429/AD5439/AD5449.
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5429/AD5439/AD5449, the SYNC
line is taken low (PC7). Data appearing on the MOSI output is
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
MC68HC11*
80C51
Figure 53. MCH68HC11/68L11-to-AD5429/AD5439/AD5449 Interface
Figure 52. 80C51/80L51-to-AD5429/AD5439/AD5449 Interface
*
MOSI
P1.1
SCK
RxD
TxD
PC7
SCLK
SDIN
SYNC
SYNC
SDIN
AD5429/AD5439/
SCLK
AD5429/AD5439/
AD5449*
AD5449*
Rev. D | Page 23 of 28
valid on the falling edge of SCK. Serial data from the 68HC11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
To load data to the DAC, leave PC7 low after the first eight bits
are transferred and perform a second serial write operation to
the DAC. PC7 is taken high at the end of this procedure.
If the user wants to verify the data previously written to the input
shift register, the SDO line can be connected to MISO of the
MC68HC11, and, with SYNC low, the shift register clocks data
out on the rising edges of SCLK.
MICROWIRE-to-AD5429/AD5439/AD5449 Interface
Figure 54 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC SCLK.
PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 microcontroller user manual for
more information. In this example, the I/O port, RA1, is used to
provide a SYNC signal and enable the serial port of the DAC. This
microcontroller transfers only eight bits of data during each serial
transfer operation; therefore, two consecutive write operations
are required.
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
MICROWIRE*
PIC16C6x/7x*
Figure 55. PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface
Figure 54. MICROWIRE-to-AD5429/AD5439/AD5449 Interface
SCK/RC3
SDI/RC4
Figure 55
RA1
SK
SO
CS
shows the connection diagram.
AD5429/AD5439/AD5449
AD5429/AD5439/
AD5429/AD5439/
SCLK
SDIN
SYNC
SCLK
SDIN
SYNC
AD5449*
AD5449*