AD9786 Analog Devices, AD9786 Datasheet - Page 29

• Manufacturer Part Number: AD9786
• Manufacturer: Analog Devices

Specifications of AD9786

• Resolution (bits): 16bit
• Dac Update Rate: 500MSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

Low Setup/Hold Mode
(DATACLK Input, Data Recovery Off)
Some applications might require that digital input data be
synchronized with the DATACLK input, rather than DACCLK.
For these applications, the AD9786 can be programmed for low
setup/hold mode by entering the values in Table 26 into the SPI
registers. With data recovery off and the MODSYNC bit set to
Logic 1, the AD9786 latches data in upon the rising or falling
edge of DATACLK input, depending on the state of DCLKPOL.
External Sync Mode
In the external sync mode, the DATACLK is programmed as an
input but is not used. Applying a DATACLK input while in this
mode has no effect. The digital input data is synchronized solely
to the DACCLK input. With 1× interpolation, the data input is
latched upon every rising edge of DACCLK. The challenge is
that the user has no way of knowing exactly which edge is the
latching edge when the interpolating filters are in use. In 2×, 4×,
and 8× interpolation modes, the latching edge of DACCLK is
every 2
With the 2 ns keep-out window, shown in Figure 53, there is a
strong possibility of violating setup and hold times, especially at
high speeds. It is recommended that users sense the DAC output
noise floor for setup and hold violations. If setup and hold is violated,
DCLKPOL can be switched. The effect of switching the state of
DCLKPOL is that the latching edge is moved by one, two, or four
DACCLK cycles if the AD9786 is in 2×, 4×, or 8× interpolation
modes, respectively. Note that in this mode, the DATAADJ bits
have no effect.
Figure 51. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 0
Figure 52. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 1
t
ST
t
ST
= 3.0ns MIN
= 2.0ns MIN
nd
, 4
t
S
th
= –1.1ns MIN
, or 8
t
t
HT
t
S
HT
th
= –1.8ns MIN
= 0.0ns MIN
= 1.0ns MIN
edge, respectively.
t
H
= 2.8ns MIN
t
H
= 3.1ns MIN
DACCLK
DATACLK
DATA
DACCLK
DATACLK
DATA
IN
IN
IN
IN
Rev. B | Page 29 of 56
Note that when using the AD9786 in external sync mode with
1× interpolation, that functionality is identical to master mode,
except that DATACLK out is not available. That is, with
DATACLKPOL = 0, data is latched on the falling edge of DACCLK,
and with DATACLKPOL = 1, data is latched on the rising edge
of DACCLK.
DATAADJUST Synchronization
When designing the digital interface for high speed DACs, care
must be taken to ensure that the DAC input data meets setup
and hold requirements. Often, compensation must be used in
the clock delay path to the digital engine driving the DAC. The
AD9786 has the on-chip capability to vary the latching edge of
DACCLK. With the interpolation function enabled, this allows
the user the choice of multiple edges upon which to latch the
data. For instance, if the AD9786 is using 8× interpolation, the
user can latch from one of eight edges before the rising edge of
DATACLK, or seven edges after this rising edge. The specific
edge upon which data is latched is controlled by SPI Register
0x05, Bits 7:4. Table 27 shows the relationship of the latching
edge of DACCLK and DATACLK with the various settings of
the DATAADJ bits.
Table 27. DATAADJ Values for Latching Edge Sync
Bit 7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SPI Register 0x05
t
S
Bit 6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
= –300ps MIN
Figure 53. External Sync Mode with 2× Interpolation
Bit 5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
t
H
= 2.9ns MIN
Latching Edge Write DATACLK
0
+1
+2
+3
+4
+5
+6
+7
–8
–7
–6
–5
–4
–3
–2
–1
DACCLK
DATA
AD9786
IN