AD5381 Analog Devices, AD5381 Datasheet
AD5381
Specifications of AD5381
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AD5381 Summary of contents
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... REG6 12 c REG6 INPUT DAC REG7 REG7 12 m REG7 12 c REG7 ×5 LDAC Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD5381 REFGND REFOUT/REFIN SIGNAL_GND (×5) 1.25V/2.5V REFERENCE 12 DAC 0 VOUT0 DAC 1 VOUT1 VOUT2 R VOUT3 R VOUT4 12 ...
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... AD5381 TABLE OF CONTENTS General Description ......................................................................... 3 Specifications..................................................................................... 4 AD5381-5 Specifications ............................................................. 4 AD5381-3 Specifications ............................................................. 6 AC Characteristics........................................................................ 7 Timing Characteristics..................................................................... 8 Serial Interface Timing ................................................................ Serial Interface Timing........................................................ 10 Parallel Interface Timing ........................................................... 11 Absolute Maximum Ratings.......................................................... 13 ESD Caution................................................................................ 13 Pin Configuration and Function Descriptions........................... 14 Terminology .................................................................................... 17 Typical Performance Characteristics ........................................... 18 Functional Description .................................................................. 21 DAC Architecture— ...
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... The AD5381 is a complete, single-supply, 40-channel, 12-bit DAC available in a 100-lead LQFP package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5381 includes a programmable internal 1.25 V/2 ppm/°C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode, which allows optimization of the amplifier slew rate ...
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... MΩ min Typically 100 MΩ ±10 μA max Typically ± AVDD/2 V min/max Enabled via CR8 in the AD5381 control register, CR10 selects the reference voltage 2.495/2.505 V min/max At ambient, optimized for 2.5 V operation. CR10 = 1 1.22/1.28 V min/max CR10 = 0 ±10 ppm/°C max Temperature Range: +25° ...
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... AD5381-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from VOUT = AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5381-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5381 control register; operating the AD5381-5 with a 1.25 V reference will lead to degraded accuracy specifications. 1 AD5381-5 Unit Test Conditions/Comments ...
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... MΩ min Typically 100 MΩ ±10 μA max Typically ± AVDD/2 V min/max Enabled via CR8 in the AD5381 control register CR10 selects the reference voltage. 1.245/1.255 V min/max At ambient; optimized for 1.25 V operation; CR10 = 0 2.47/2.53 V min/max CR10 = 1 ±10 ppm/° ...
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... Accuracy guaranteed from VOUT = AVDD – 50 mV. 3 Guaranteed by characterization, not production tested. 4 Default on the AD5381-3 is 1.25 V. Programmable to 2.5 V via CR10 in the AD5381 control register; operating the AD5381-3 with a 2.5 V reference will lead to degraded accuracy specifications and limited input code range CHARACTERISTICS AVDD = 3.6 V ...
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... AD5381 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING DVDD = 2 5.5 V; AVDD 3.6 V; AGND = DGND = 0 V; all specifications unless otherwise noted. MIN MAX Table Parameter Limit MIN ...
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... DB0 DB23 NOP CONDITION DB23 SELECTED REGISTER DATA CLOCKED OUT DB0 DB23 INPUT WORD FOR DAC DB23 INPUT WORD FOR DAC N Rev Page AD5381 DB0 DB0 DB0 DB0 ...
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... AD5381 SERIAL INTERFACE TIMING DVDD = 2 5.5 V; AVDD = 3.6 V; AGND = DGND = 0 V; all specifications T unless otherwise noted. Table Parameter Limit MIN MAX F 400 SCL 100 300 ...
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... BUSY rising edge to LDAC falling edge ns min LDAC falling edge to DAC output response time μs typ DAC output settling time, boost mode off ns min CLR pulse width low μsmax CLR pulse activation time Rev Page AD5381 MIN MAX ...
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... AD5381 REG0, REG1, A5...A0 DB11...DB0 BUSY LDAC VOUT1 LDAC VOUT2 CLR VOUT LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. Figure 7. Parallel Interface Timing Diagram Rev ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. Rev Page AD5381 ...
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... Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and should be decoupled with a 0.1 μF ceramic capacitor and 10 μF tantalum capacitor. Operating range for the AD5381 5.5 V; operating range for the AD5381 3.6 V. DGND Ground for All Digital Circuitry ...
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... Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word on the AD5381. A5–A0 Parallel Address Inputs are decoded to address one of the AD5381’s 40 input channels. Used in conjunction with the REG1 and REG0 pins to determine the destination register for the input data. ...
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... AD5381 Mnemonic Function PD Power-Down (Level Sensitive, Active High used to place the device in low power mode, where the analog current consumption is reduced to 2 μA and the digital current consumption is reduced to 20 μA. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 kΩ ...
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... Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) in the linear region of the transfer function, expressed in mV. Offset error is measured on the AD5381-5 with Code 32 loaded into the DAC register, and on the AD5381-3 with Code 64. Gain Error Gain Error is specified in the linear region of the output range between VOUT = 10 mV and VOUT = AVDD – ...
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... VOUT Rev Page REFIN = 1.25V 0 512 1024 1536 2048 2560 3072 INPUT CODE Figure 12. Typical AD5381-3 INL Plot AVDD = DVDD = 1.25V REF T = 25°C A 14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 5nV 100 150 ...
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... Rev Page 2.5V VOUT AVDD Figure 18. Power-Up Transient –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 REFERENCE DRIFT (ppm/°C) Figure 19. REFOUT Temperature Coefficient PD AVDD = DVDD = 2.5V REF VOUT T = 25°C A EXITS HARDWARE PD TO MIDSCALE Figure 20. Exiting Hardware Power-Down AD5381 5.0 ...
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... REFOUT = 2.5V 200 REFOUT = 1.25V 100 0 100 1k FREQUENCY (Hz) Figure 23. REFOUT Noise Spectral Density V = 2.5V REF T = 25° Figure 24. AD5381-3 Output Amplifier Source and Sink Capability 2.456 AVDD = 2.5V REF T = 25°C A 2.455 2.454 2.453 2.452 2.451 2.450 2.449 1.50 1.75 2.00 = 25°C 10k 100k Rev ...
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... V is recommended for the AD5381-5, and 1.25 V for the AD5381-3. DATA DECODING The AD5381 contains a 12-bit data bus, DB11 to DB0. Depend- ing on the value of REG1 and REG0 (see Table 11), this data is loaded into the addressed DAC input registers, offset (c) AVDD registers, or gain (m) registers ...
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... AD5381 ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5381 contains a number of special function registers (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0. Table 15. SFR Register Functions (REG1 = 0, REG0 = 0) R ...
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... MON_OUT pin assumes its normal DAC output function. CR6: Thermal Monitor Function. When enabled, this function is used to monitor the internal die temperature of the AD5381. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function can be used to ...
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... AD5381 Table 18. AD5381 Channel Monitor Decoding REG1 REG0 ...
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... BUSY AND LDAC FUNCTIONS BUSY is a digital CMOS output that indicates the status of the AD5381. The value of x2, the internal data loaded to the DAC data register, is calculated each time the user writes new data to the corresponding x1 registers. During the calculation of x2, the BUSY output goes low ...
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... A1 A0 Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5381 in standalone and daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 19 This pin selects whether the data write is to the register when toggle mode is enabled. With toggle disabled, this bit should be set select the A data register ...
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... SDO. Figure 30 shows the readback sequence. For example, to read back the m register of Channel 0 on the AD5381, the following sequence should be implemented. First, write 0x404XXX to the AD5381 input register. This configures the AD5381 for read mode with the m register of Channel 0 selected. Note that Data Bits DB11 to DB0 are don’ ...
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... START condition followed by the 7-bit slave address. When idle, the AD5381 waits for a START condition followed by its slave address. The LSB of the address word is the Read/ 2 Write ( bit. The AD5381 is a receive only device; when C operating communicating with the AD5381 After receiving the 2 ...
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... SDA REG1 REG0 MSB MOST SIGNIFICANT DATA BYTE AD1 AD0 R ACK BY MSB AD538x LSB MSB ACK BY AD538x 2 Figure 31. 4-Byte AD5381 Write Operation AD1 AD0 R ACK BY MSB AD538x LSB MSB ACK BY AD538x DATA FOR CHANNEL "N" ACK BY ...
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... AD5381. See Table 11. Pin A5 to Pin A0 Each of the 40 DAC channels can be individually addressed. Pin DB11 to Pin DB0 The AD5381 accepts a straight 12-bit parallel word on DB11 to DB0, where DB11 is the MSB and DB0 is the LSB. AD1 AD0 ...
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... The lower address lines from the processor are connected the AD5381. The upper address lines are decoded to provide LDAC signal for the AD5381. The fast interface timing of the AD5381 allows direct interface to a wide variety of microcontrollers and DSPs, as shown in Figure 35. ...
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... MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. 8XC51 AD5381 to ADSP-2101/ADSP-2103 Figure 38 shows a serial interface between the AD5381 and the AD5381 ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should SER/PAR be set up to operate in SPORT transmit alternate framing mode. ...
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... The printed circuit board on which the AD5381 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5381 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point established as close to the device as possible ...
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... A write with REG1 = REG0 = 0 and 001100 specifies a control register write. The toggle mode function is enabled in groups of eight channels using Bit CR4 to Bit CR0 in the control register. See the AD5381 control register description. Figure 42 shows a block diagram of toggle mode implementation. Each of the 40 DAC channels on the AD5381 contain an A and B data register ...
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... ATTENUATOR 12 ATTENUATOR 1n–1 ATTENUATOR 1n ATTENUATOR N:1 MULTIPLEXER AD5381, 40-CHANNEL, 12-BIT DAC CONTROLLER 16-BIT ADC Figure 43. OADM Using the AD5381 as Part of an Optical Attenuator Rev Page VOUT 12-BIT DAC LDAC CONTROL INPUT DWDM OUT AWG FIBRE TIA/LOG AMP (AD8304/AD8305) ADG731 (40:1 MUX) AD7671 ...
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... AD5381 GROUP A GROUP B GROUP C CHNLS 0–39 CHNLS 40–79 CHNLS 80–119 FIFO DATA LOAD GROUP A FIFO DATA LOAD 1.6μs 1.6μs GROUP B OUTPUT UPDATE 14.4μs TIME FOR GROUP A 14.4μs GROUP D GROUP E GROUP F GROUP G CHNLS CHNLS CHNLS CHNLS 120–159 160–199 200–239 240– ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Resolution AD5381BST-3 12 Bits AD5381BST-3-REEL 12 Bits 1 AD5381BSTZ-3 12 Bits 1 AD5381BSTZ-3-REEL 12 Bits AD5381BST-5 12 Bits AD5381BST-5-REEL 12 Bits 1 AD5381BSTZ-5 12 Bits 1 AD5381BSTZ-5-REEL 12 Bits EVAL-AD5381EB Pb-free part Standard Specification as defined by Philips. 1.60 MAX 0.75 100 1 0.60 0.45 0.20 0.09 7° ...
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... AD5381 NOTES Rev Page ...
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... NOTES Rev Page AD5381 ...
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... AD5381 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...