AD5381 Analog Devices, AD5381 Datasheet - Page 35

• Manufacturer Part Number: AD5381
• Description: 40-Channel 12-Bit 3 V/5 V Single-Supply Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5381

• Resolution (bits): 12bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par,Ser,SPI

OPTICAL ATTENUATORS
Based on its high channel count, high resolution, monotonic
behavior, and high level of integration, the AD5381 is ideally
targeted at optical attenuation applications used in dynamic
gain equalizers, variable optical attenuators (VOAs), and optical
add-drop multiplexers (OADMs). In these applications, each
wavelength is individually extracted using an arrayed wave
guide; its power is monitored using a photodiode, transimped-
ance amplifier and ADC in a closed-loop control system. The
AD5381 controls the optical attenuator for each wavelength,
ensuring that the power is equalized in all wavelengths before
being multiplexed onto the fiber. This prevents information loss
and saturation from occurring at amplification stages further
along the fiber.
INPUT
A/B
DATA
DWDM
IN
REGISTER
FIBRE
INPUT
AWG
Figure 43. OADM Using the AD5381 as Part of an Optical Attenuator
11
12
1n–1
1n
PORTS
ADD
OPTICAL
REGISTER
REGISTER
SWITCH
DATA
DATA
Figure 42. Toggle Mode Function
A
B
CONTROLLER
40-CHANNEL,
PORTS
12-BIT DAC
DROP
AD5381,
Rev. B | Page 35 of 40
ATTENUATOR
ATTENUATOR
ATTENUATOR
ATTENUATOR
REGISTER
DAC
UTILIZING FIFO
The AD5381 FIFO mode optimizes total system update rates
in applications where a large number of channels need to be
updated. FIFO mode is only available when parallel interface
mode is selected. The FIFO EN pin is used to enable the FIFO.
The status of FIFO EN is sampled during the initialization
sequence. Therefore, the FIFO status can only be changed by
resetting the device.
In a telescope that provides for the cancel-lation of atmospheric
distortion, for example, a large number of channels need to be
updated in a short period of time. In such systems, as many as
400 channels need to be updated within 40 μs. Four-hundred
channels require the use of 10 AD5381s. With FIFO mode
enabled, the data write cycle time is 40 ns; therefore, each group
consisting of 40 channels can be fully loaded in 1.6 μs. In FIFO
mode, a complete group of 40 chan-nels will update in 14.4 μs.
The time taken to update all 400 channels is
14.4 μs + 9 × 1.6 μs = 28.8 μs.
Figure 44 shows the FIFO operation scheme.
N:1 MULTIPLEXER
16-BIT ADC
PHOTODIODES
12-BIT DAC
TIA/LOG AMP
(AD8304/AD8305)
ADG731
(40:1 MUX)
AD7671
(0V TO 5V, 1MSPS)
AWG
VOUT
LDAC
CONTROL INPUT
FIBRE
DWDM
OUT
AD5381