AD5383 Analog Devices, AD5383 Datasheet
AD5383
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AD5383 Summary of contents
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... REG 7 REG REG REG 7 ×4 LDAC Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113© 2004–2010 Analog Devices, Inc. All rights reserved. AD5383 REFGND REFOUT/REFIN SIGNAL GND (×4) 1.25V/2.5V REFERENCE 12 DAC 0 V OUT ...
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... AD5383 TABLE OF CONTENTS General Description ......................................................................... 3 Specifications ..................................................................................... 4 AD5383-5 Specifications ............................................................. 4 AD5383-3 Specifications ............................................................. 6 AC Characteristics ........................................................................ 7 Timing Characteristics ..................................................................... 8 Serial Interface Timing ................................................................ Serial Interface Timing ........................................................ 10 Parallel Interface Timing ........................................................... 11 Absolute Maximum Ratings .......................................................... 13 ESD CAUTION .......................................................................... 13 Pin Configuration and Function Descriptions ........................... 14 Terminology .................................................................................... 17 Typical Performance Characteristics ........................................... 18 Functional Description .................................................................. 21 DAC Architecture— ...
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... MON_OUT pin for external monitoring; and an output amplifier boost mode that allows optimization of the amplifier slew rate. The AD5383 features • Double-buffered parallel interface with pulse width. • ...
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... MΩ min Typically 100 MΩ ±10 μA max Typically ± min/max DD Enabled via CR8 in the AD5383 control register, CR10 selects the reference voltage 2.495/2.505 V min/max At ambient; optimized for 2.5 V operation; CR10 = 1 1.22/1.28 V min/max 1.25 V reference selected; CR10 = 0 ±10 ppm/°C max Temperature range: +25° ...
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... AD5383-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C. 2 Accuracy guaranteed from OUT DD 3 Guaranteed by characterization, not production tested. 4 Default on the AD5383-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5383 control register; operating the AD5383-5 with a 1.25 V reference leads to degraded accuracy specifications. 1 AD5383-5 Unit 0.4 V max DV – 1 ...
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... MΩ min Typically 100 MΩ ±10 μA max Typically ± min/max DD Enabled via CR8 in the AD5383 control register, CR10 selects the reference voltage 1.245/1.255 V min/max At ambient; optimized for 1.25 V operation; CR10 = 0 2.47/2.53 V min/max 2.5 V reference enabled; CR10 = 1 ±10 ppm/°C typ Temperature range: +25° ...
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... AV DD OUT 3 Guaranteed by characterization, not production tested. 4 Default on the AD5383-3 is 1.25 V. Programmable to 2.5 V via CR10 in the AD5383 control register; operating the AD5383-3 with a 2.5 V reference leads to degraded accuracy specifications and limited input code range CHARACTERISTICS Table 5 ...
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... AD5383 TIMING CHARACTERISTICS SERIAL INTERFACE TIMING 3.6 V; AGND = DGND = 0 V; all specifications noted. Table Parameter Limit MIN MAX ...
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... DB0 DB23 NOP CONDITION DB23 SELECTED REGISTER DATA CLOCKED OUT DB0 DB23 INPUT WORD FOR DAC N DB23 INPUT WORD FOR DAC N Rev Page AD5383 DB0 DB0 DB0 DB0 ...
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... AD5383 SERIAL INTERFACE TIMING 3.6 V; AGND = DGND = 0 V; all specifications noted. Table Parameter Limit MIN MAX F 400 SCL 100 300 300 ...
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... BUSY rising edge to LDAC falling edge ns min LDAC falling edge to DAC output response time μs max DAC output settling time ns min CLR pulse width low μs max CLR pulse activation time ) and timed from a voltage level of 1 Rev Page AD5383 unless otherwise MIN MAX ...
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... AD5383 REG0, REG1, A4..A0 DB11..DB0 BUSY LDAC V OUT LDAC V OUT CLR OUT 1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY Figure 7. Parallel Interface Timing Diagram Rev ...
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... V of this specification is not implied. Exposure to absolute DD maximum rating conditions for extended periods may affect + 0.3 V device reliability Rev Page AD5383 ...
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... Analog Supply Pins. Each group of eight channels has a separate AV DD internally and should be decoupled with a 0.1 μF ceramic capacitor and a 10 μF tantalum capacitor. Operating range for the AD5383 5.5 V; operating range for the AD5383 3.6 V. DGND Ground for All Digital Circuitry. ...
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... Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word on the AD5383 Parallel Address Inputs are decoded to address one of the AD5383’s 40 input channels. Used in conjunction with the REG1 and REG0 pins to determine the destination register for the input data. ...
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... AD5383 Mnemonic Function PD Power Down (Level Sensitive, Active High used to place the device in low power mode where the device consumes 2 μA analog supply current and 20 μA digital supply current. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or will provide a 100 kΩ ...
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... Offset error is a measure of the difference between V and V (ideal) in the linear region of the transfer function, OUT expressed in mV. Offset error is measured on the AD5383-5 with Code 32 loaded into the DAC register, and on the AD5383-3 with Code 64. Gain Error Gain Error is specified in the linear region of the output range ...
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... DD Rev Page REFIN = 1.25V 0 0 512 1024 1536 2048 2560 3072 INPUT CODE Figure 12. Typical AD5383-3 INL Plot 1.25V REF T = 25°C A 14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 5nV ...
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... OUT Rev Page OUT AV DD Figure 18. Power-Up Transient –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 REFERENCE DRIFT (ppm/°C) Figure 19. REFOUT Temperature Coefficient REF V T OUT EXITS HARDWARE PD TO MIDSCALE Figure 20. Exiting Hardware Power-Down AD5383 = 2.5V = 25°C A ...
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... A 4 3/4 SCALE FULL-SCALE 3 MIDSCALE ZERO-SCALE 1/4 SCALE –1 –40 –20 –10 –5 – CURRENT (mA) Figure 24. AD5383-3 Output Amplifier Source and Sink Capability 2.5V REF T = 25°C A 14ns/SAMPLE NUMBER 0 50 100 150 200 250 300 350 400 SAMPLE NUMBER Figure 25. Adjacent Channel DAC-to-DAC Crosstalk ...
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... DAC, using the internal m and c registers, which hold the correction factors. All channels are double buffered, allowing synchronous updating of all channels using the LDAC pin. Figure 27 shows a block diagram of a single channel on the AD5383. The digital input transfer function for each DAC can be represented – [(m + 2)/ 2 × ...
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... AD5383 ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) The AD5383 contains a number of special function registers (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bit A4 to Address Bit A0. Table 15. SFR Register Functions (REG1 = 0, REG0 = ...
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... CR11 = 0. Amplifier output is 100 kΩ to ground. CR10: REF Select. This bit selects the operating internal reference for the AD5383. CR12 is programmed as follows: CR10 = 1: Internal reference is 2.5 V (AD5383-5 default), the recommended operating reference for AD5383-5. CR10 = 0: Internal reference is 1.25 V (AD5383-3 default), the recommended operating reference for AD5383-3. ...
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... REG1 REG0 OUT V 1 OUT AD5383 V 30 CHANNEL OUT V 31 MONITOR OUT MON_IN1 DECODING MON_OUT MON_IN2 MON_IN3 MON_IN4 CHANNEL ADDRESS DB11–DB6 Figure 28. Channel Monitor Decoding Rev Page DB8 DB7 ...
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... BUSY AND LDAC FUNCTIONS BUSY is a digital CMOS output that indicates the status of the AD5383. The value of x2, the internal data loaded to the DAC data register, is calculated each time the user writes new data to the corresponding x1 registers. During the calculation of x2, the BUSY output goes low ...
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... Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5383 in standalone and daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 19. A /B. When toggle mode is enabled, this pin selects whether the 2 C data write is to the register. With toggle disabled, this bit should be set to zero to select the A data register ...
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... SDO. Figure 30 shows the readback sequence. For example, to read back the m register of Channel 0 on the AD5383, the following sequence should be implemented. First, write 0x404XXX to the AD5383 input register. This configures the AD5383 for read mode with the m register of Channel 0 selected. Note that Data Bits DB11 to DB0 are don’ ...
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... SDA and SCL facilitate communication between the AD5383 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagram that incorporates three different modes of operation. In selecting the I ...
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... AD538x POINTER BYTE LSB ACK BY AD538x LEAST SIGNIFICANT BYTE ACK BY AD538x POINTER BYTE FOR CHANNEL "N" LSB ACK BY AD538x LEAST SIGNIFICANT DATA BYTE LSB ACK BY AD538x LEAST SIGNIFICANT DATA BYTE AD5383 STOP COND BY MASTER STOP COND BY MASTER ...
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... Pin A4 to Pin A0 are latched; data present on the data bus is loaded into the selected input registers. REG0, REG1 Pins The REG0 and REG1 pins determine the destination register of the data being written to the AD5383. See Table 11. Pins Each of the 32 DAC channels can be addressed individually. Pins DB11 to DB0 The AD5383 accepts a straight 12-bit parallel word on DB11 to DB0, where DB11 is the MSB and DB0 is the LSB ...
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... the AD5383. The upper address lines are decoded to provide LDAC signal for the AD5383. The fast interface timing of the AD5383 allows direct interface to a wide variety of microcontrollers and DSPs, as shown in AD5383 to MC68HC11 ...
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... The AD5383 requires its data to be MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. AD5383 to ADSP-2101/ADSP-2103 Figure 38 shows a serial interface between the AD5383 and the AD5383 DD ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should SER/PAR be set up to operate in SPORT transmit alternate framing mode ...
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... The printed circuit board on which the AD5383 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5383 system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point established as close to the device as possible ...
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... Register Write/Read section. Figure 42 of toggle mode implementation. Each of the 32 DAC channels on the AD5383 contain an A and B data register. Note that the B registers can only be loaded when toggle mode is enabled. The sequence of events when configuring the AD5383 for toggle mode is: 1 ...
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... DAC CONTROLLER 16-BIT ADC Figure 43. OADM Using the AD5383 as Part of an Optical Attenuator ance amplifier and ADC in a closed-loop control system. The AD5383 controls the optical attenuator for each wavelength, ensuring that the power is equalized in all wavelengths before being multiplexed onto the fiber. This prevents information loss and saturation from occurring at amplification stages further along the fiber ...
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... TIME FOR GROUP A 11.5μs systems, as many as 320 channels need to be updated within 25 μ μs. 320 channels require the use of 10 AD5383s. With FIFO mode enabled, the data write cycle time is 40 ns; therefore, each group consisting of 32 channels can be fully loaded in 1.28 μs. In FIFO mode, a complete group of 32 channels updates in 11.5 μ ...
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... Output DD Range Range Channels –40°C to +85° –40°C to +85° Rev Page 14.20 14.00 SQ 13.80 TOP VIEW 51 50 0.27 0.22 0.17 Linearity Package Error Description ±1 LSB 100-Lead LQFP ±1 LSB 100-Lead LQFP AD5383 Package Option ST-100-1 ST-100-1 ...
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... AD5383 NOTES Rev Page ...
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... NOTES Rev Page AD5383 ...
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... AD5383 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03734–0–4/10(B) Rev Page ...