AD9742 Analog Devices, AD9742 Datasheet
AD9742
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AD9742 Summary of contents
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... The AD9742 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9742’s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output ...
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... DAC Transfer Function ............................................................. 13 Analog Outputs........................................................................... 13 Digital Inputs .............................................................................. 14 Clock Input.................................................................................. 14 DAC Timing................................................................................ 15 Power Dissipation....................................................................... 15 Applying the AD9742 ................................................................ 16 Differential Coupling Using a Transformer................................ 16 Differential Coupling Using an Op Amp ................................ 16 Single-Ended, Unbuffered Voltage Output ............................. 17 Single-Ended, Buffered Voltage Output Configuration ........ 17 Power and Grounding Considerations, Power Supply Rejection ...................................................................................... 17 Evaluation Board ...
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... V 1 MΩ 0.5 MHz 0 ppm of FSR/°C ±50 ppm of FSR/°C ±100 ppm of FSR/°C ±50 ppm/°C 3.3 3.6 V 3.3 3.6 V 3.3 3 135 145 mW 145 FSR/V +0. FSR/V +85 °C = 100 MSPS and MHz. CLOCK OUT AD9742 ...
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... AD9742 DYNAMIC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX minated, unless otherwise noted. Table 2 Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) CLOCK 1 Output Settling Time (t ) (to 0.1%) ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time (10% to 90%) ...
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... OUTFS Min 2.1 −10 −10 2.0 1.5 1.5 0 0.75 0 LPW 0.1% Figure 2. Timing Diagram Rev Page Min Typ Max Typ Max 3 0 0.9 +10 + 1.5 2.25 1.5 0.1% AD9742 Unit dBc dBc dBc dBc Unit V V µA µ ...
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... AD9742 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect to Min AVDD ACOM −0.3 DVDD DCOM −0.3 CLKVDD CLKCOM −0.3 ACOM DCOM −0.3 ACOM CLKCOM −0.3 DCOM CLKCOM −0.3 AVDD DVDD −3.9 AVDD CLKVDD −3.9 DVDD CLKVDD −3.9 CLOCK, SLEEP DCOM −0.3 Digital Inputs, MODE DCOM − ...
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... Clock Common. Rev Page DB5 ADJ PIN 1 INDICATOR DB4 2 23 REFIO DVDD 3 22 ACOM AD9742 21 IOUTA DB3 4 DB2 5 TOP VIEW 20 IOUTB DB1 6 (Not to Scale) 19 ACOM (LSB) DB0 7 18 AVDD AVDD CONNECT Figure 4. 32-Lead LFCSP Pin Configuration AD9742 ...
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... It is measured as the difference be- tween the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone For MIN MAX 3.3V REFLO AVDD ACOM 150pF AD9742 PMOS CURRENT SOURCE ARRAY IOUTA SEGMENTED SWITCHES LSB IOUTB SWITCHES FOR DB11–DB3 MODE LATCHES ...
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... OUT Figure 10. SFDR vs 210 MSPS OUT 20mA 10mA 5mA (MHz) OUT Figure 11. SFDR vs. f and MSPS and 0 dBFS OUT OUTFS AD9742 50 60 –6dBFS ...
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... AD9742 65MSPS 80 125MSPS 75 165MSPS 210MSPS (LFCSP –25 –20 –15 –10 A (dBFS) OUT Figure 12. Single-Tone SFDR vs. A OUT 125MSPS (LFCSP) 65MSPS 80 75 165MSPS (LFCSP 125MSPS 55 210MSPS (LFCSP) 210MSPS 50 45 –25 –20 –15 –10 A (dBFS) OUT Figure 13. Single-Tone SFDR vs. A ...
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... Figure 20. Dual-Tone SFDR f = 78MSPS CLOCK f = 15.0MHz OUT1 f = 15.4MHz OUT2 f = 15.8MHz OUT3 f = 16.2MHz OUT4 SFDR = 75dBc AMPLITUDE = 0dBFS FREQUENCY (MHz) Figure 21. Four-Tone SFDR – V DIFF OUTA OUTB IOUTA IOUTA V OUTA IOUTB IOUTB V OUTB R LOAD 50Ω R MODE LOAD 50Ω AD9742 36 36 ...
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... AD9742 FUNCTIONAL DESCRIPTION Figure 22 shows a simplified block diagram of the AD9742. The AD9742 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing full-scale current (I ). The array is divided into 31 equal currents that OUTFS make up the five most significant bits (MSBs) ...
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... REFERENCE CONTROL AMPLIFIER The AD9742 contains a control amplifier that is used to regulate the full-scale output current The control amplifier is OUTFS configured as a V-I converter, as shown in Figure 24, so that its current output determined by the ratio of the V REF an external resistor stated in Equation 4. I SET ...
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... As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration will result in the optimum dc linearity. Note that the INL/DNL specifications for the AD9742 are measured with IOUTA maintained at a vir- tual ground via an op amp. IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance ...
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... Level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω AVDD. This digital input also contains an active pull-down circuit that ensures that the AD9742 remains enabled if this input is left disconnected. The AD9742 takes less than power down and approximately 5 µs to power back up. ...
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... R DIFFERENTIAL COUPLING USING AN OP AMP An op amp can also be used to perform a differential-to-single- ended conversion, as shown in Figure 32. The AD9742 is configured with two equal load resistors, R differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration ...
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... In this case, AVDD, which is the positive analog supply for both the AD9742 and the op amp, is also used to level shift the differential output of the AD9742 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this applicatio AD9742 225Ω ...
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... Figure 36, becomes Proper grounding and decoupling should be a primary objec- tive in any high speed, high resolution system. The AD9742 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system ...
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... The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9742 with either the internal or external reference or to exercise the power-down feature. J1 ...
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... DB11 4 25 DB10 MODE DB10 5 24 DB9 AVDD DB9 6 23 DB8 DB8 RESERVED 7 22 DB7 IOUTA DB7 DB6 DB6 IOUTB AD9742 20 9 DB5 ACOM DB5 19 10 DB4 DB4 DB3 DB3 FS ADJ 12 17 DB2 REFIO DB2 13 16 DB1 DB1 REFLO 14 ...
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... Figure 40. SOIC Evaluation Board—Primary Side Figure 41. SOIC Evaluation Board—Secondary Side Rev Page AD9742 ...
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... AD9742 Figure 42. SOIC Evaluation Board—Ground Plane Figure 43. SOIC Evaluation Board—Power Plane Rev Page ...
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... Figure 44. SOIC Evaluation Board Assembly—Primary Side Figure 45. SOIC Evaluation Board Assembly—Secondary Side Rev Page AD9742 ...
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... AD9742 L1 BEAD TB1 1 BLK C3 0.1µF TP2 TB1 2 L2 BEAD TB3 1 BLK C7 0.1µF TP4 TB3 2 L3 BEAD TB4 1 BLK C9 0.1µF TP6 TB4 100Ω 100Ω DB13X DB12X DB11X DB10X DB9X DB8X DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X CKEXTX ...
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... Rev Page DVDD CVDD C19 C19 0.1 0.1µF R11 50Ω DNP C13 JP8 IOUT – 1T JP9 DNP C12 R10 50Ω CVDD C20 C35 10µF 0.1µF 16V S5 AGND C34 0.1µF R6 50Ω AD9742 C32 0.1µF S3 AGND ...
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... AD9742 Figure 49. LFCSP Evaluation Board Layout—Primary Side Figure 50. LFCSP Evaluation Board Layout—Secondary Side Rev Page ...
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... Figure 51. LFCSP Evaluation Board Layout—Ground Plane Figure 52. LFCSP Evaluation Board Layout—Power Plane Rev Page AD9742 ...
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... AD9742 Figure 53. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 54. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev Page ...
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... PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 56. 28-Lead Standard Small Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) Rev Page 6.40 BSC 8 ° 0.75 0 ° 0.60 0.45 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) × 45° 0.25 (0.0098) 8° 0° 1.27 (0.0500) 0.40 (0.0157) AD9742 ...
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... AD9742ARURL7 −40°C to +85°C 2 AD9742ARUZ −40°C to +85°C 2 AD9742ARUZRL7 −40°C to +85°C AD9742ACP −40°C to +85°C AD9742ACPRL7 −40°C to +85°C 2 AD9742ACPZ −40°C to +85°C AD9742ACPZRL7 2 −40°C to +85°C AD9742-EB AD9742ACP-PCB Small Outline IC ...
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... NOTES Rev Page AD9742 ...
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... AD9742 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. C02912–0–6/04(B) Rev Page ...