AD9742 Analog Devices, AD9742 Datasheet - Page 7

• Manufacturer Part Number: AD9742
• Manufacturer: Analog Devices

Specifications of AD9742

• Resolution (bits): 12bit
• Dac Update Rate: 210MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
SOIC/TSSOP
Pin No.
1
2 to 11
12
13, 14
15
16
17
18
19
20
21
22
23
24
25
N/A
26
27
28
N/A
N/A
N/A
N/A
Figure 3. 28-Lead SOIC and TSSOP Pin Configuration
(MSB) DB11
(LSB) DB0
LFCSP
Pin No.
27
28 to 32,
1, 2, 4 to 6
7
8, 9
25
N/A
23
24
N/A
19, 22
20
21
N/A
17, 18
16
15
10, 26
3
N/A
12
13
11
14
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
NC
NC
10
11
12
13
14
1
2
3
4
5
6
7
8
9
NC = NO CONNECT
(Not to Scale)
AD9742
TOP VIEW
Mnemonic
DB11
DB10 to
DB1
DB0
N/C
SLEEP
REFLO
REFIO
FS ADJ
NC
ACOM
IOUTB
IOUTA
RESERVED
AVDD
MODE
CMODE
DCOM
DVDD
CLOCK
CLK+
CLK−
CLKVDD
CLKCOM
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
DAC Current Output. Full-scale current when all data bits are 1s.
Reserved. Do not connect to common or supply.
Description
Most Significant Data Bit (MSB).
Data Bits 10 to 1.
Least Significant Data Bit (LSB).
No Internal Connection.
Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie
REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie
REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
No Internal Connection.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
Analog Supply Voltage (3.3 V).
Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and
float CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations
on-chip).
Digital Common.
Digital Supply Voltage (3.3 V).
Clock Input. Data latched on positive edge of clock.
Differential Clock Input.
Differential Clock Input.
Clock Supply Voltage (3.3 V).
Clock Common.
Rev. B | Page 7 of 32
(LSB) DB0 7
Figure 4. 32-Lead LFCSP Pin Configuration
DVDD 3
DB5 1
DB4 2
DB3 4
DB2 5
DB1 6
NC 8
NC = NO CONNECT
(Not to Scale)
PIN 1
INDICATOR
AD9742
TOP VIEW
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
AD9742